Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __DTS_HISTB_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __DTS_HISTB_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /* clocks provided by core CRG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define HISTB_OSC_CLK			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define HISTB_APB_CLK			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define HISTB_AHB_CLK			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define HISTB_UART1_CLK			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define HISTB_UART2_CLK			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define HISTB_UART3_CLK			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define HISTB_I2C0_CLK			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define HISTB_I2C1_CLK			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HISTB_I2C2_CLK			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define HISTB_I2C3_CLK			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HISTB_I2C4_CLK			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HISTB_I2C5_CLK			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HISTB_SPI0_CLK			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HISTB_SPI1_CLK			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HISTB_SPI2_CLK			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HISTB_SCI_CLK			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HISTB_FMC_CLK			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HISTB_MMC_BIU_CLK		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HISTB_MMC_CIU_CLK		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HISTB_MMC_DRV_CLK		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HISTB_MMC_SAMPLE_CLK		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HISTB_SDIO0_BIU_CLK		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HISTB_SDIO0_CIU_CLK		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HISTB_SDIO0_DRV_CLK		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HISTB_SDIO0_SAMPLE_CLK		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HISTB_PCIE_AUX_CLK		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HISTB_PCIE_PIPE_CLK		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HISTB_PCIE_SYS_CLK		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HISTB_PCIE_BUS_CLK		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HISTB_ETH0_MAC_CLK		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HISTB_ETH0_MACIF_CLK		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HISTB_ETH1_MAC_CLK		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HISTB_ETH1_MACIF_CLK		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HISTB_COMBPHY1_CLK		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HISTB_USB2_BUS_CLK		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HISTB_USB2_PHY_CLK		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HISTB_USB2_UTMI_CLK		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HISTB_USB2_12M_CLK		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HISTB_USB2_48M_CLK		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HISTB_USB2_OTG_UTMI_CLK		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HISTB_USB2_PHY1_REF_CLK		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HISTB_USB2_PHY2_REF_CLK		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HISTB_COMBPHY0_CLK		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HISTB_USB3_BUS_CLK		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HISTB_USB3_UTMI_CLK		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HISTB_USB3_PIPE_CLK		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HISTB_USB3_SUSPEND_CLK		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HISTB_USB3_BUS_CLK1		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HISTB_USB3_UTMI_CLK1		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HISTB_USB3_PIPE_CLK1		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HISTB_USB3_SUSPEND_CLK1		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* clocks provided by mcu CRG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HISTB_MCE_CLK			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HISTB_IR_CLK			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HISTB_TIMER01_CLK		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HISTB_LEDC_CLK			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define HISTB_UART0_CLK			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define HISTB_LSADC_CLK			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif	/* __DTS_HISTB_CLOCK_H */