Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2015 Hisilicon Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Bintian Wang <bintian.wang@huawei.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef __DT_BINDINGS_CLOCK_HI6220_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define __DT_BINDINGS_CLOCK_HI6220_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /* clk in Hi6220 AO (always on) controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define HI6220_NONE_CLOCK	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /* fixed rate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define HI6220_REF32K		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define HI6220_CLK_TCXO		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define HI6220_MMC1_PAD		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define HI6220_MMC2_PAD		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define HI6220_MMC0_PAD		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define HI6220_PLL_BBP		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define HI6220_PLL_GPU		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define HI6220_PLL1_DDR		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define HI6220_PLL_SYS		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define HI6220_PLL_SYS_MEDIA	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define HI6220_DDR_SRC		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define HI6220_PLL_MEDIA	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define HI6220_PLL_DDR		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* fixed factor clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define HI6220_300M		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define HI6220_150M		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define HI6220_PICOPHY_SRC	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define HI6220_MMC0_SRC_SEL	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define HI6220_MMC1_SRC_SEL	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define HI6220_MMC2_SRC_SEL	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define HI6220_VPU_CODEC	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define HI6220_MMC0_SMP		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define HI6220_MMC1_SMP		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define HI6220_MMC2_SMP		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* gate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define HI6220_WDT0_PCLK	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define HI6220_WDT1_PCLK	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define HI6220_WDT2_PCLK	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define HI6220_TIMER0_PCLK	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define HI6220_TIMER1_PCLK	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define HI6220_TIMER2_PCLK	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define HI6220_TIMER3_PCLK	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define HI6220_TIMER4_PCLK	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define HI6220_TIMER5_PCLK	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define HI6220_TIMER6_PCLK	33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define HI6220_TIMER7_PCLK	34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define HI6220_TIMER8_PCLK	35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define HI6220_UART0_PCLK	36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define HI6220_RTC0_PCLK	37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define HI6220_RTC1_PCLK	38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define HI6220_AO_NR_CLKS	39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /* clk in Hi6220 systrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /* gate clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define HI6220_MMC0_CLK		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define HI6220_MMC0_CIUCLK	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define HI6220_MMC1_CLK		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define HI6220_MMC1_CIUCLK	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define HI6220_MMC2_CLK		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define HI6220_MMC2_CIUCLK	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define HI6220_USBOTG_HCLK	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define HI6220_CLK_PICOPHY	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define HI6220_HIFI		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define HI6220_DACODEC_PCLK	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define HI6220_EDMAC_ACLK	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define HI6220_CS_ATB		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define HI6220_I2C0_CLK		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define HI6220_I2C1_CLK		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define HI6220_I2C2_CLK		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define HI6220_I2C3_CLK		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define HI6220_UART1_PCLK	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define HI6220_UART2_PCLK	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define HI6220_UART3_PCLK	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define HI6220_UART4_PCLK	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define HI6220_SPI_CLK		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define HI6220_TSENSOR_CLK	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define HI6220_MMU_CLK		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define HI6220_HIFI_SEL		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define HI6220_MMC0_SYSPLL	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define HI6220_MMC1_SYSPLL	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define HI6220_MMC2_SYSPLL	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define HI6220_MMC0_SEL		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define HI6220_MMC1_SEL		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define HI6220_BBPPLL_SEL	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define HI6220_MEDIA_PLL_SRC	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define HI6220_MMC2_SEL		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define HI6220_CS_ATB_SYSPLL	33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) /* mux clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define HI6220_MMC0_SRC		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define HI6220_MMC0_SMP_IN	35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define HI6220_MMC1_SRC		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define HI6220_MMC1_SMP_IN	37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HI6220_MMC2_SRC		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HI6220_MMC2_SMP_IN	39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define HI6220_HIFI_SRC		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HI6220_UART1_SRC	41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define HI6220_UART2_SRC	42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define HI6220_UART3_SRC	43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HI6220_UART4_SRC	44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define HI6220_MMC0_MUX0	45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HI6220_MMC1_MUX0	46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HI6220_MMC2_MUX0	47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HI6220_MMC0_MUX1	48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HI6220_MMC1_MUX1	49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HI6220_MMC2_MUX1	50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* divider clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define HI6220_CLK_BUS		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HI6220_MMC0_DIV		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HI6220_MMC1_DIV		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HI6220_MMC2_DIV		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HI6220_HIFI_DIV		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HI6220_BBPPLL0_DIV	56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HI6220_CS_DAPB		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HI6220_CS_ATB_DIV	58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* gate clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HI6220_DAPB_CLK		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define HI6220_SYS_NR_CLKS	60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* clk in Hi6220 media controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* gate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define HI6220_DSI_PCLK		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define HI6220_G3D_PCLK		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define HI6220_ACLK_CODEC_VPU	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define HI6220_ISP_SCLK		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define HI6220_ADE_CORE		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define HI6220_MED_MMU		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define HI6220_CFG_CSI4PHY	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HI6220_CFG_CSI2PHY	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define HI6220_ISP_SCLK_GATE	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define HI6220_ISP_SCLK_GATE1	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define HI6220_ADE_CORE_GATE	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HI6220_CODEC_VPU_GATE	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define HI6220_MED_SYSPLL	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* mux clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HI6220_1440_1200	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define HI6220_1000_1200	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define HI6220_1000_1440	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* divider clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define HI6220_CODEC_JPEG	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define HI6220_ISP_SCLK_SRC	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define HI6220_ISP_SCLK1	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HI6220_ADE_CORE_SRC	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define HI6220_ADE_PIX_SRC	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define HI6220_G3D_CLK		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define HI6220_CODEC_VPU_SRC	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define HI6220_MEDIA_NR_CLKS	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* clk in Hi6220 power controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* gate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define HI6220_PLL_GPU_GATE	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define HI6220_PLL1_DDR_GATE	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define HI6220_PLL_DDR_GATE	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define HI6220_PLL_MEDIA_GATE	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define HI6220_PLL0_BBP_GATE	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* divider clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define HI6220_DDRC_SRC		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define HI6220_DDRC_AXI1	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define HI6220_POWER_NR_CLKS	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* clk in Hi6220 acpu sctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define HI6220_ACPU_SFT_AT_S		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #endif