^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Device Tree binding constants for HiSilicon Hi3670 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2018 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __DT_BINDINGS_CLOCK_HI3670_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __DT_BINDINGS_CLOCK_HI3670_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* clk in stub clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define HI3670_CLK_STUB_CLUSTER0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define HI3670_CLK_STUB_CLUSTER1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define HI3670_CLK_STUB_GPU 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define HI3670_CLK_STUB_DDR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define HI3670_CLK_STUB_DDR_VOTE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HI3670_CLK_STUB_DDR_LIMIT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define HI3670_CLK_STUB_NUM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* clk in crg clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HI3670_CLKIN_SYS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HI3670_CLKIN_REF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HI3670_CLK_FLL_SRC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HI3670_CLK_PPLL0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HI3670_CLK_PPLL1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HI3670_CLK_PPLL2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HI3670_CLK_PPLL3 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HI3670_CLK_PPLL4 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HI3670_CLK_PPLL6 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HI3670_CLK_PPLL7 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HI3670_CLK_PPLL_PCIE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HI3670_CLK_PCIEPLL_REV 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HI3670_CLK_SCPLL 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HI3670_PCLK 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HI3670_CLK_UART0_DBG 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HI3670_CLK_UART6 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HI3670_OSC32K 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HI3670_OSC19M 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HI3670_CLK_480M 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HI3670_CLK_INVALID 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HI3670_CLK_DIV_SYSBUS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HI3670_CLK_FACTOR_MMC 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HI3670_CLK_SD_SYS 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HI3670_CLK_SDIO_SYS 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HI3670_CLK_DIV_A53HPM 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HI3670_CLK_DIV_320M 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HI3670_PCLK_GATE_UART0 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HI3670_CLK_FACTOR_UART0 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HI3670_CLK_FACTOR_USB3PHY_PLL 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HI3670_CLK_GATE_ABB_USB 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HI3670_CLK_GATE_UFSPHY_REF 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HI3670_ICS_VOLT_HIGH 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HI3670_ICS_VOLT_MIDDLE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HI3670_VENC_VOLT_HOLD 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HI3670_VDEC_VOLT_HOLD 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HI3670_EDC_VOLT_HOLD 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HI3670_CLK_ISP_SNCLK_FAC 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HI3670_CLK_FACTOR_RXDPHY 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HI3670_AUTODIV_SYSBUS 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HI3670_AUTODIV_EMMC0BUS 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HI3670_PCLK_ANDGT_MMC1_PCIE 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HI3670_CLK_GATE_VCODECBUS_GT 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HI3670_CLK_ANDGT_SD 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HI3670_CLK_SD_SYS_GT 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HI3670_CLK_ANDGT_SDIO 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define HI3670_CLK_SDIO_SYS_GT 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define HI3670_CLK_A53HPM_ANDGT 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define HI3670_CLK_320M_PLL_GT 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HI3670_CLK_ANDGT_UARTH 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define HI3670_CLK_ANDGT_UARTL 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define HI3670_CLK_ANDGT_UART0 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define HI3670_CLK_ANDGT_SPI 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define HI3670_CLK_ANDGT_PCIEAXI 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define HI3670_CLK_DIV_AO_ASP_GT 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define HI3670_CLK_GATE_CSI_TRANS 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define HI3670_CLK_GATE_DSI_TRANS 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define HI3670_CLK_ANDGT_PTP 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HI3670_CLK_ANDGT_OUT0 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define HI3670_CLK_ANDGT_OUT1 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HI3670_CLKGT_DP_AUDIO_PLL_AO 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define HI3670_CLK_ANDGT_VDEC 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define HI3670_CLK_ANDGT_VENC 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define HI3670_CLK_ISP_SNCLK_ANGT 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define HI3670_CLK_ANDGT_RXDPHY 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define HI3670_CLK_ANDGT_ICS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define HI3670_AUTODIV_DMABUS 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HI3670_CLK_MUX_SYSBUS 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define HI3670_CLK_MUX_VCODECBUS 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HI3670_CLK_MUX_SD_SYS 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HI3670_CLK_MUX_SD_PLL 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define HI3670_CLK_MUX_SDIO_SYS 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define HI3670_CLK_MUX_SDIO_PLL 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HI3670_CLK_MUX_A53HPM 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HI3670_CLK_MUX_320M 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HI3670_CLK_MUX_UARTH 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HI3670_CLK_MUX_UARTL 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define HI3670_CLK_MUX_UART0 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define HI3670_CLK_MUX_I2C 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HI3670_CLK_MUX_SPI 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HI3670_CLK_MUX_PCIEAXI 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define HI3670_CLK_MUX_AO_ASP 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HI3670_CLK_MUX_VDEC 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define HI3670_CLK_MUX_VENC 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define HI3670_CLK_ISP_SNCLK_MUX0 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HI3670_CLK_ISP_SNCLK_MUX1 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define HI3670_CLK_ISP_SNCLK_MUX2 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HI3670_CLK_MUX_RXDPHY_CFG 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HI3670_CLK_MUX_ICS 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HI3670_CLK_DIV_CFGBUS 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HI3670_CLK_DIV_MMC0BUS 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HI3670_CLK_DIV_MMC1BUS 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define HI3670_PCLK_DIV_MMC1_PCIE 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define HI3670_CLK_DIV_VCODECBUS 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define HI3670_CLK_DIV_SD 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HI3670_CLK_DIV_SDIO 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HI3670_CLK_DIV_UARTH 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HI3670_CLK_DIV_UARTL 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HI3670_CLK_DIV_UART0 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HI3670_CLK_DIV_I2C 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HI3670_CLK_DIV_SPI 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HI3670_CLK_DIV_PCIEAXI 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define HI3670_CLK_DIV_AO_ASP 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HI3670_CLK_DIV_CSI_TRANS 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HI3670_CLK_DIV_DSI_TRANS 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HI3670_CLK_DIV_PTP 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define HI3670_CLK_DIV_CLKOUT0_PLL 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define HI3670_CLK_DIV_CLKOUT1_PLL 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define HI3670_CLKDIV_DP_AUDIO_PLL_AO 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define HI3670_CLK_DIV_VDEC 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define HI3670_CLK_DIV_VENC 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define HI3670_CLK_ISP_SNCLK_DIV0 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define HI3670_CLK_ISP_SNCLK_DIV1 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define HI3670_CLK_ISP_SNCLK_DIV2 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define HI3670_CLK_DIV_ICS 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define HI3670_PPLL1_EN_ACPU 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define HI3670_PPLL2_EN_ACPU 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HI3670_PPLL3_EN_ACPU 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define HI3670_PPLL1_GT_CPU 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define HI3670_PPLL2_GT_CPU 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define HI3670_PPLL3_GT_CPU 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HI3670_CLK_GATE_PPLL2_MEDIA 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define HI3670_CLK_GATE_PPLL3_MEDIA 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define HI3670_CLK_GATE_PPLL4_MEDIA 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HI3670_CLK_GATE_PPLL6_MEDIA 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HI3670_CLK_GATE_PPLL7_MEDIA 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define HI3670_PCLK_GPIO0 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define HI3670_PCLK_GPIO1 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define HI3670_PCLK_GPIO2 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define HI3670_PCLK_GPIO3 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define HI3670_PCLK_GPIO4 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define HI3670_PCLK_GPIO5 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define HI3670_PCLK_GPIO6 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HI3670_PCLK_GPIO7 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define HI3670_PCLK_GPIO8 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define HI3670_PCLK_GPIO9 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define HI3670_PCLK_GPIO10 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define HI3670_PCLK_GPIO11 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define HI3670_PCLK_GPIO12 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define HI3670_PCLK_GPIO13 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define HI3670_PCLK_GPIO14 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define HI3670_PCLK_GPIO15 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define HI3670_PCLK_GPIO16 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define HI3670_PCLK_GPIO17 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define HI3670_PCLK_GPIO20 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define HI3670_PCLK_GPIO21 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define HI3670_PCLK_GATE_DSI0 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define HI3670_PCLK_GATE_DSI1 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define HI3670_HCLK_GATE_USB3OTG 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define HI3670_ACLK_GATE_USB3DVFS 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define HI3670_HCLK_GATE_SDIO 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define HI3670_PCLK_GATE_PCIE_SYS 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define HI3670_PCLK_GATE_PCIE_PHY 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define HI3670_PCLK_GATE_MMC1_PCIE 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define HI3670_PCLK_GATE_MMC0_IOC 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define HI3670_PCLK_GATE_MMC1_IOC 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define HI3670_CLK_GATE_DMAC 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define HI3670_CLK_GATE_VCODECBUS2DDR 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define HI3670_CLK_CCI400_BYPASS 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define HI3670_CLK_GATE_CCI400 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define HI3670_CLK_GATE_SD 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define HI3670_HCLK_GATE_SD 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define HI3670_CLK_GATE_SDIO 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define HI3670_CLK_GATE_A57HPM 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define HI3670_CLK_GATE_A53HPM 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define HI3670_CLK_GATE_PA_A53 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define HI3670_CLK_GATE_PA_A57 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define HI3670_CLK_GATE_PA_G3D 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define HI3670_CLK_GATE_GPUHPM 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define HI3670_CLK_GATE_PERIHPM 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define HI3670_CLK_GATE_AOHPM 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define HI3670_CLK_GATE_UART1 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define HI3670_CLK_GATE_UART4 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define HI3670_PCLK_GATE_UART1 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define HI3670_PCLK_GATE_UART4 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define HI3670_CLK_GATE_UART2 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define HI3670_CLK_GATE_UART5 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define HI3670_PCLK_GATE_UART2 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define HI3670_PCLK_GATE_UART5 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define HI3670_CLK_GATE_UART0 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define HI3670_CLK_GATE_I2C3 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define HI3670_CLK_GATE_I2C4 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define HI3670_CLK_GATE_I2C7 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define HI3670_PCLK_GATE_I2C3 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define HI3670_PCLK_GATE_I2C4 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define HI3670_PCLK_GATE_I2C7 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define HI3670_CLK_GATE_SPI1 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define HI3670_CLK_GATE_SPI4 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define HI3670_PCLK_GATE_SPI1 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define HI3670_PCLK_GATE_SPI4 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define HI3670_CLK_GATE_USB3OTG_REF 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define HI3670_CLK_GATE_USB2PHY_REF 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define HI3670_CLK_GATE_PCIEAUX 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define HI3670_ACLK_GATE_PCIE 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define HI3670_CLK_GATE_MMC1_PCIEAXI 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define HI3670_CLK_GATE_PCIEPHY_REF 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define HI3670_CLK_GATE_PCIE_DEBOUNCE 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define HI3670_CLK_GATE_PCIEIO 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define HI3670_CLK_GATE_PCIE_HP 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define HI3670_CLK_GATE_AO_ASP 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define HI3670_PCLK_GATE_PCTRL 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define HI3670_CLK_CSI_TRANS_GT 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define HI3670_CLK_DSI_TRANS_GT 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define HI3670_CLK_GATE_PWM 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define HI3670_ABB_AUDIO_EN0 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define HI3670_ABB_AUDIO_EN1 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define HI3670_ABB_AUDIO_GT_EN0 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define HI3670_ABB_AUDIO_GT_EN1 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define HI3670_CLK_GATE_DP_AUDIO_PLL_AO 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define HI3670_PERI_VOLT_HOLD 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define HI3670_PERI_VOLT_MIDDLE 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define HI3670_CLK_GATE_ISP_SNCLK0 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define HI3670_CLK_GATE_ISP_SNCLK1 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define HI3670_CLK_GATE_ISP_SNCLK2 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define HI3670_CLK_GATE_RXDPHY0_CFG 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define HI3670_CLK_GATE_RXDPHY1_CFG 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define HI3670_CLK_GATE_RXDPHY2_CFG 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define HI3670_CLK_GATE_TXDPHY0_CFG 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define HI3670_CLK_GATE_TXDPHY0_REF 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define HI3670_CLK_GATE_TXDPHY1_CFG 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define HI3670_CLK_GATE_TXDPHY1_REF 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define HI3670_CLK_GATE_MEDIA_TCXO 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* clk in sctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define HI3670_CLK_ANDGT_IOPERI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define HI3670_CLKANDGT_ASP_SUBSYS_PERI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define HI3670_CLK_ANGT_ASP_SUBSYS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define HI3670_CLK_MUX_UFS_SUBSYS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define HI3670_CLK_MUX_CLKOUT0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define HI3670_CLK_MUX_CLKOUT1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define HI3670_CLK_MUX_ASP_SUBSYS_PERI 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define HI3670_CLK_MUX_ASP_PLL 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define HI3670_CLK_DIV_AOBUS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define HI3670_CLK_DIV_UFS_SUBSYS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define HI3670_CLK_DIV_IOPERI 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define HI3670_CLK_DIV_CLKOUT0_TCXO 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define HI3670_CLK_DIV_CLKOUT1_TCXO 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define HI3670_CLK_ASP_SUBSYS_PERI_DIV 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define HI3670_CLK_DIV_ASP_SUBSYS 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define HI3670_PPLL0_EN_ACPU 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define HI3670_PPLL0_GT_CPU 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define HI3670_CLK_GATE_PPLL0_MEDIA 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define HI3670_PCLK_GPIO18 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define HI3670_PCLK_GPIO19 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define HI3670_CLK_GATE_SPI 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define HI3670_PCLK_GATE_SPI 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define HI3670_CLK_GATE_UFS_SUBSYS 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define HI3670_CLK_GATE_UFSIO_REF 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define HI3670_PCLK_AO_GPIO0 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define HI3670_PCLK_AO_GPIO1 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define HI3670_PCLK_AO_GPIO2 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define HI3670_PCLK_AO_GPIO3 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define HI3670_PCLK_AO_GPIO4 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define HI3670_PCLK_AO_GPIO5 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define HI3670_PCLK_AO_GPIO6 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define HI3670_CLK_GATE_OUT0 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define HI3670_CLK_GATE_OUT1 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define HI3670_PCLK_GATE_SYSCNT 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define HI3670_CLK_GATE_SYSCNT 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define HI3670_CLK_GATE_ASP_SUBSYS_PERI 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define HI3670_CLK_GATE_ASP_SUBSYS 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define HI3670_CLK_GATE_ASP_TCXO 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define HI3670_CLK_GATE_DP_AUDIO_PLL 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* clk in pmuctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define HI3670_GATE_ABB_192 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* clk in pctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define HI3670_GATE_UFS_TCXO_EN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define HI3670_GATE_USB_TCXO_EN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* clk in iomcu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define HI3670_CLK_GATE_I2C0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define HI3670_CLK_GATE_I2C1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define HI3670_CLK_GATE_I2C2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define HI3670_CLK_GATE_SPI0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define HI3670_CLK_GATE_SPI2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define HI3670_CLK_GATE_UART3 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define HI3670_CLK_I2C0_GATE_IOMCU 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define HI3670_CLK_I2C1_GATE_IOMCU 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define HI3670_CLK_I2C2_GATE_IOMCU 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define HI3670_CLK_SPI0_GATE_IOMCU 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define HI3670_CLK_SPI2_GATE_IOMCU 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define HI3670_CLK_UART3_GATE_IOMCU 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define HI3670_CLK_GATE_PERI0_IOMCU 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* clk in media1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define HI3670_CLK_GATE_VIVOBUS_ANDGT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define HI3670_CLK_ANDGT_EDC0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define HI3670_CLK_ANDGT_LDI0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define HI3670_CLK_ANDGT_LDI1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define HI3670_CLK_MMBUF_PLL_ANDGT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define HI3670_PCLK_MMBUF_ANDGT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define HI3670_CLK_MUX_VIVOBUS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define HI3670_CLK_MUX_EDC0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define HI3670_CLK_MUX_LDI0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define HI3670_CLK_MUX_LDI1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define HI3670_CLK_SW_MMBUF 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define HI3670_CLK_DIV_VIVOBUS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define HI3670_CLK_DIV_EDC0 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define HI3670_CLK_DIV_LDI0 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define HI3670_CLK_DIV_LDI1 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define HI3670_ACLK_DIV_MMBUF 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define HI3670_PCLK_DIV_MMBUF 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define HI3670_ACLK_GATE_NOC_DSS 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define HI3670_PCLK_GATE_NOC_DSS_CFG 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define HI3670_PCLK_GATE_MMBUF_CFG 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define HI3670_PCLK_GATE_DISP_NOC_SUBSYS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define HI3670_ACLK_GATE_DISP_NOC_SUBSYS 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define HI3670_PCLK_GATE_DSS 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define HI3670_ACLK_GATE_DSS 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define HI3670_CLK_GATE_VIVOBUSFREQ 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define HI3670_CLK_GATE_EDC0 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define HI3670_CLK_GATE_LDI0 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define HI3670_CLK_GATE_LDI1FREQ 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define HI3670_CLK_GATE_BRG 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define HI3670_ACLK_GATE_ASC 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define HI3670_CLK_GATE_DSS_AXI_MM 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define HI3670_CLK_GATE_MMBUF 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define HI3670_PCLK_GATE_MMBUF 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define HI3670_CLK_GATE_ATDIV_VIVO 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* clk in media2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define HI3670_CLK_GATE_VDECFREQ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define HI3670_CLK_GATE_VENCFREQ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define HI3670_CLK_GATE_ICSFREQ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #endif /* __DT_BINDINGS_CLOCK_HI3670_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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