^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016-2017 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __DTS_HI3660_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __DTS_HI3660_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* fixed rate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define HI3660_CLKIN_SYS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define HI3660_CLKIN_REF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define HI3660_CLK_FLL_SRC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define HI3660_CLK_PPLL0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define HI3660_CLK_PPLL1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define HI3660_CLK_PPLL2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define HI3660_CLK_PPLL3 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HI3660_CLK_SCPLL 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define HI3660_PCLK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HI3660_CLK_UART0_DBG 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HI3660_CLK_UART6 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HI3660_OSC32K 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HI3660_OSC19M 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HI3660_CLK_480M 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HI3660_CLK_INV 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* clk in crgctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HI3660_FACTOR_UART3 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HI3660_CLK_FACTOR_MMC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HI3660_CLK_GATE_I2C0 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HI3660_CLK_GATE_I2C1 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HI3660_CLK_GATE_I2C2 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HI3660_CLK_GATE_I2C6 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HI3660_CLK_DIV_SYSBUS 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HI3660_CLK_DIV_320M 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HI3660_CLK_DIV_A53 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HI3660_CLK_GATE_SPI0 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HI3660_CLK_GATE_SPI2 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HI3660_PCIEPHY_REF 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HI3660_CLK_ABB_USB 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HI3660_HCLK_GATE_SDIO0 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HI3660_HCLK_GATE_SD 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HI3660_CLK_GATE_AOMM 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HI3660_PCLK_GPIO0 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HI3660_PCLK_GPIO1 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HI3660_PCLK_GPIO2 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HI3660_PCLK_GPIO3 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HI3660_PCLK_GPIO4 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HI3660_PCLK_GPIO5 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HI3660_PCLK_GPIO6 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HI3660_PCLK_GPIO7 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HI3660_PCLK_GPIO8 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HI3660_PCLK_GPIO9 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HI3660_PCLK_GPIO10 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HI3660_PCLK_GPIO11 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HI3660_PCLK_GPIO12 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HI3660_PCLK_GPIO13 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HI3660_PCLK_GPIO14 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HI3660_PCLK_GPIO15 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HI3660_PCLK_GPIO16 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HI3660_PCLK_GPIO17 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HI3660_PCLK_GPIO18 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HI3660_PCLK_GPIO19 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HI3660_PCLK_GPIO20 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HI3660_PCLK_GPIO21 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HI3660_CLK_GATE_SPI3 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define HI3660_CLK_GATE_I2C7 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define HI3660_CLK_GATE_I2C3 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define HI3660_CLK_GATE_SPI1 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HI3660_CLK_GATE_UART1 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define HI3660_CLK_GATE_UART2 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define HI3660_CLK_GATE_UART4 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define HI3660_CLK_GATE_UART5 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define HI3660_CLK_GATE_I2C4 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define HI3660_CLK_GATE_DMAC 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define HI3660_PCLK_GATE_DSS 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define HI3660_ACLK_GATE_DSS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define HI3660_CLK_GATE_LDI1 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HI3660_CLK_GATE_LDI0 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define HI3660_CLK_GATE_VIVOBUS 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HI3660_CLK_GATE_EDC0 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define HI3660_CLK_GATE_TXDPHY0_CFG 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define HI3660_CLK_GATE_TXDPHY0_REF 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define HI3660_CLK_GATE_TXDPHY1_CFG 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define HI3660_CLK_GATE_TXDPHY1_REF 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define HI3660_ACLK_GATE_USB3OTG 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define HI3660_CLK_GATE_SPI4 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HI3660_CLK_GATE_SD 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define HI3660_CLK_GATE_SDIO0 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HI3660_CLK_GATE_UFS_SUBSYS 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HI3660_PCLK_GATE_DSI0 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define HI3660_PCLK_GATE_DSI1 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define HI3660_ACLK_GATE_PCIE 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HI3660_PCLK_GATE_PCIE_SYS 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HI3660_CLK_GATE_PCIEAUX 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HI3660_PCLK_GATE_PCIE_PHY 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HI3660_CLK_ANDGT_LDI0 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define HI3660_CLK_ANDGT_LDI1 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define HI3660_CLK_ANDGT_EDC0 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HI3660_CLK_GATE_UFSPHY_GT 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HI3660_CLK_ANDGT_MMC 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define HI3660_CLK_ANDGT_SD 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HI3660_CLK_A53HPM_ANDGT 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define HI3660_CLK_ANDGT_SDIO 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define HI3660_CLK_ANDGT_UART0 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HI3660_CLK_ANDGT_UART1 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define HI3660_CLK_ANDGT_UARTH 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HI3660_CLK_ANDGT_SPI 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HI3660_CLK_VIVOBUS_ANDGT 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HI3660_CLK_AOMM_ANDGT 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HI3660_CLK_320M_PLL_GT 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HI3660_AUTODIV_EMMC0BUS 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define HI3660_AUTODIV_SYSBUS 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define HI3660_CLK_GATE_UFSPHY_CFG 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define HI3660_CLK_GATE_UFSIO_REF 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HI3660_CLK_MUX_SYSBUS 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HI3660_CLK_MUX_UART0 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HI3660_CLK_MUX_UART1 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HI3660_CLK_MUX_UARTH 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HI3660_CLK_MUX_SPI 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HI3660_CLK_MUX_I2C 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HI3660_CLK_MUX_MMC_PLL 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define HI3660_CLK_MUX_LDI1 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HI3660_CLK_MUX_LDI0 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HI3660_CLK_MUX_SD_PLL 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HI3660_CLK_MUX_SD_SYS 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define HI3660_CLK_MUX_EDC0 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define HI3660_CLK_MUX_SDIO_SYS 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define HI3660_CLK_MUX_SDIO_PLL 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define HI3660_CLK_MUX_VIVOBUS 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define HI3660_CLK_MUX_A53HPM 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define HI3660_CLK_MUX_320M 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define HI3660_CLK_MUX_IOPERI 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define HI3660_CLK_DIV_UART0 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define HI3660_CLK_DIV_UART1 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define HI3660_CLK_DIV_UARTH 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define HI3660_CLK_DIV_MMC 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HI3660_CLK_DIV_SD 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define HI3660_CLK_DIV_EDC0 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define HI3660_CLK_DIV_LDI0 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define HI3660_CLK_DIV_SDIO 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HI3660_CLK_DIV_LDI1 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define HI3660_CLK_DIV_SPI 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define HI3660_CLK_DIV_VIVOBUS 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HI3660_CLK_DIV_I2C 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HI3660_CLK_DIV_UFSPHY 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define HI3660_CLK_DIV_CFGBUS 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define HI3660_CLK_DIV_MMC0BUS 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define HI3660_CLK_DIV_MMC1BUS 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define HI3660_CLK_DIV_UFSPERI 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define HI3660_CLK_DIV_AOMM 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define HI3660_CLK_DIV_IOPERI 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define HI3660_VENC_VOLT_HOLD 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HI3660_PERI_VOLT_HOLD 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define HI3660_CLK_GATE_VENC 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define HI3660_CLK_GATE_VDEC 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define HI3660_CLK_ANDGT_VENC 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define HI3660_CLK_ANDGT_VDEC 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define HI3660_CLK_MUX_VENC 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define HI3660_CLK_MUX_VDEC 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define HI3660_CLK_DIV_VENC 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define HI3660_CLK_DIV_VDEC 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define HI3660_CLK_FAC_ISP_SNCLK 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define HI3660_CLK_GATE_ISP_SNCLK0 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define HI3660_CLK_GATE_ISP_SNCLK1 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define HI3660_CLK_GATE_ISP_SNCLK2 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define HI3660_CLK_ANGT_ISP_SNCLK 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define HI3660_CLK_MUX_ISP_SNCLK 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define HI3660_CLK_DIV_ISP_SNCLK 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* clk in pmuctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define HI3660_GATE_ABB_192 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* clk in pctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define HI3660_GATE_UFS_TCXO_EN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define HI3660_GATE_USB_TCXO_EN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* clk in sctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define HI3660_PCLK_AO_GPIO0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define HI3660_PCLK_AO_GPIO1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define HI3660_PCLK_AO_GPIO2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define HI3660_PCLK_AO_GPIO3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define HI3660_PCLK_AO_GPIO4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define HI3660_PCLK_AO_GPIO5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define HI3660_PCLK_AO_GPIO6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define HI3660_PCLK_GATE_MMBUF 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define HI3660_CLK_GATE_DSS_AXI_MM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define HI3660_PCLK_MMBUF_ANDGT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define HI3660_CLK_MMBUF_PLL_ANDGT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define HI3660_CLK_FLL_MMBUF_ANDGT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define HI3660_CLK_SYS_MMBUF_ANDGT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define HI3660_CLK_GATE_PCIEPHY_GT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define HI3660_ACLK_MUX_MMBUF 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define HI3660_CLK_SW_MMBUF 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define HI3660_CLK_DIV_AOBUS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define HI3660_PCLK_DIV_MMBUF 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define HI3660_ACLK_DIV_MMBUF 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define HI3660_CLK_DIV_PCIEPHY 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* clk in iomcu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define HI3660_CLK_I2C0_IOMCU 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define HI3660_CLK_I2C1_IOMCU 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define HI3660_CLK_I2C2_IOMCU 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define HI3660_CLK_I2C6_IOMCU 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define HI3660_CLK_IOMCU_PERI0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* clk in stub clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define HI3660_CLK_STUB_CLUSTER0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define HI3660_CLK_STUB_CLUSTER1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define HI3660_CLK_STUB_GPU 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define HI3660_CLK_STUB_DDR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define HI3660_CLK_STUB_NUM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #endif /* __DTS_HI3660_CLOCK_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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