^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2012-2013 Hisilicon Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2012-2013 Linaro Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Xin Li <li.xin@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __DTS_HI3620_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __DTS_HI3620_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define HI3620_NONE_CLOCK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* fixed rate & fixed factor clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define HI3620_OSC32K 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define HI3620_OSC26M 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HI3620_PCLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define HI3620_PLL_ARM0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HI3620_PLL_ARM1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HI3620_PLL_PERI 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HI3620_PLL_USB 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HI3620_PLL_HDMI 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HI3620_PLL_GPU 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HI3620_RCLK_TCXO 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HI3620_RCLK_CFGAXI 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HI3620_RCLK_PICO 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* mux clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HI3620_TIMER0_MUX 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HI3620_TIMER1_MUX 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HI3620_TIMER2_MUX 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HI3620_TIMER3_MUX 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HI3620_TIMER4_MUX 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HI3620_TIMER5_MUX 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HI3620_TIMER6_MUX 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HI3620_TIMER7_MUX 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HI3620_TIMER8_MUX 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HI3620_TIMER9_MUX 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HI3620_UART0_MUX 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HI3620_UART1_MUX 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HI3620_UART2_MUX 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HI3620_UART3_MUX 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HI3620_UART4_MUX 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HI3620_SPI0_MUX 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HI3620_SPI1_MUX 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HI3620_SPI2_MUX 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HI3620_SAXI_MUX 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HI3620_PWM0_MUX 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HI3620_PWM1_MUX 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HI3620_SD_MUX 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HI3620_MMC1_MUX 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HI3620_MMC1_MUX2 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HI3620_G2D_MUX 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HI3620_VENC_MUX 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HI3620_VDEC_MUX 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HI3620_VPP_MUX 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HI3620_EDC0_MUX 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HI3620_LDI0_MUX 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HI3620_EDC1_MUX 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HI3620_LDI1_MUX 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HI3620_RCLK_HSIC 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HI3620_MMC2_MUX 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HI3620_MMC3_MUX 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* divider clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define HI3620_SHAREAXI_DIV 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define HI3620_CFGAXI_DIV 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define HI3620_SD_DIV 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HI3620_MMC1_DIV 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define HI3620_HSIC_DIV 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define HI3620_MMC2_DIV 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define HI3620_MMC3_DIV 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* gate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define HI3620_TIMERCLK01 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define HI3620_TIMER_RCLK01 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define HI3620_TIMERCLK23 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HI3620_TIMER_RCLK23 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define HI3620_TIMERCLK45 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HI3620_TIMERCLK67 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define HI3620_TIMERCLK89 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define HI3620_RTCCLK 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define HI3620_KPC_CLK 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define HI3620_GPIOCLK0 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define HI3620_GPIOCLK1 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define HI3620_GPIOCLK2 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HI3620_GPIOCLK3 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define HI3620_GPIOCLK4 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HI3620_GPIOCLK5 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HI3620_GPIOCLK6 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define HI3620_GPIOCLK7 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define HI3620_GPIOCLK8 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HI3620_GPIOCLK9 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HI3620_GPIOCLK10 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HI3620_GPIOCLK11 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HI3620_GPIOCLK12 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define HI3620_GPIOCLK13 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define HI3620_GPIOCLK14 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HI3620_GPIOCLK15 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HI3620_GPIOCLK16 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define HI3620_GPIOCLK17 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HI3620_GPIOCLK18 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define HI3620_GPIOCLK19 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define HI3620_GPIOCLK20 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HI3620_GPIOCLK21 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define HI3620_DPHY0_CLK 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HI3620_DPHY1_CLK 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HI3620_DPHY2_CLK 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HI3620_USBPHY_CLK 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HI3620_ACP_CLK 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HI3620_PWMCLK0 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define HI3620_PWMCLK1 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define HI3620_UARTCLK0 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define HI3620_UARTCLK1 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HI3620_UARTCLK2 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HI3620_UARTCLK3 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HI3620_UARTCLK4 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HI3620_SPICLK0 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HI3620_SPICLK1 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HI3620_SPICLK2 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HI3620_I2CCLK0 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define HI3620_I2CCLK1 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HI3620_I2CCLK2 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HI3620_I2CCLK3 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HI3620_SCI_CLK 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define HI3620_DDRC_PER_CLK 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define HI3620_DMAC_CLK 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define HI3620_USB2DVC_CLK 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define HI3620_SD_CLK 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define HI3620_MMC_CLK1 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define HI3620_MMC_CLK2 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define HI3620_MMC_CLK3 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define HI3620_MCU_CLK 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define HI3620_SD_CIUCLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define HI3620_MMC_CIUCLK1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HI3620_MMC_CIUCLK2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define HI3620_MMC_CIUCLK3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define HI3620_NR_CLKS 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #endif /* __DTS_HI3620_CLOCK_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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