Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __DTS_HI3516CV300_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __DTS_HI3516CV300_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /* hi3516CV300 core CRG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define HI3516CV300_APB_CLK		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define HI3516CV300_UART0_CLK		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define HI3516CV300_UART1_CLK		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define HI3516CV300_UART2_CLK		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define HI3516CV300_SPI0_CLK		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define HI3516CV300_SPI1_CLK		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define HI3516CV300_FMC_CLK		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define HI3516CV300_MMC0_CLK		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HI3516CV300_MMC1_CLK		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define HI3516CV300_MMC2_CLK		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HI3516CV300_MMC3_CLK		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HI3516CV300_ETH_CLK		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HI3516CV300_ETH_MACIF_CLK	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HI3516CV300_DMAC_CLK		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HI3516CV300_PWM_CLK		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HI3516CV300_USB2_BUS_CLK	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HI3516CV300_USB2_OHCI48M_CLK	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HI3516CV300_USB2_OHCI12M_CLK	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HI3516CV300_USB2_OTG_UTMI_CLK	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HI3516CV300_USB2_HST_PHY_CLK	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HI3516CV300_USB2_UTMI0_CLK	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HI3516CV300_USB2_PHY_CLK	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* hi3516CV300 sysctrl CRG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HI3516CV300_WDT_CLK		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #endif	/* __DTS_HI3516CV300_CLOCK_H */