^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * GXBB clock tree IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __GXBB_CLKC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __GXBB_CLKC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define CLKID_SYS_PLL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CLKID_HDMI_PLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CLKID_FIXED_PLL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CLKID_FCLK_DIV2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLKID_FCLK_DIV3 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLKID_FCLK_DIV4 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLKID_FCLK_DIV5 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLKID_FCLK_DIV7 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLKID_GP0_PLL 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLKID_CLK81 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLKID_MPLL0 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLKID_MPLL1 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLKID_MPLL2 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLKID_DDR 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLKID_DOS 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLKID_ISA 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLKID_PL301 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLKID_PERIPHS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLKID_SPICC 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLKID_I2C 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLKID_SAR_ADC 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLKID_SMART_CARD 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLKID_RNG0 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLKID_UART0 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLKID_SDHC 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLKID_STREAM 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLKID_ASYNC_FIFO 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLKID_SDIO 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLKID_ABUF 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLKID_HIU_IFACE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLKID_ASSIST_MISC 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLKID_SPI 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLKID_ETH 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLKID_I2S_SPDIF 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLKID_DEMUX 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLKID_AIU_GLUE 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLKID_IEC958 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLKID_I2S_OUT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLKID_AMCLK 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLKID_AIFIFO2 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLKID_MIXER 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLKID_MIXER_IFACE 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLKID_ADC 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLKID_BLKMV 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLKID_AIU 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLKID_UART1 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLKID_G2D 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLKID_USB0 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLKID_USB1 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLKID_RESET 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLKID_NAND 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLKID_DOS_PARSER 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLKID_USB 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLKID_VDIN1 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CLKID_AHB_ARB0 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CLKID_EFUSE 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CLKID_BOOT_ROM 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CLKID_AHB_DATA_BUS 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLKID_AHB_CTRL_BUS 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CLKID_HDMI_INTR_SYNC 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CLKID_HDMI_PCLK 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLKID_USB1_DDR_BRIDGE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CLKID_USB0_DDR_BRIDGE 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLKID_MMC_PCLK 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CLKID_DVIN 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CLKID_UART2 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CLKID_SANA 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CLKID_VPU_INTR 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CLKID_SEC_AHB_AHB3_BRIDGE 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CLKID_CLK81_A53 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CLKID_VCLK2_VENCI0 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CLKID_VCLK2_VENCI1 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CLKID_VCLK2_VENCP0 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CLKID_VCLK2_VENCP1 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CLKID_GCLK_VENCI_INT0 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CLKID_GCLK_VENCI_INT 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CLKID_DAC_CLK 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CLKID_AOCLK_GATE 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CLKID_IEC958_GATE 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CLKID_ENC480P 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CLKID_RNG1 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CLKID_GCLK_VENCI_INT1 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CLKID_VCLK2_VENCLMCC 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CLKID_VCLK2_VENCL 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CLKID_VCLK_OTHER 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CLKID_EDP 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CLKID_AO_MEDIA_CPU 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CLKID_AO_AHB_SRAM 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CLKID_AO_AHB_BUS 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CLKID_AO_IFACE 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CLKID_AO_I2C 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLKID_SD_EMMC_A 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLKID_SD_EMMC_B 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLKID_SD_EMMC_C 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLKID_SAR_ADC_CLK 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLKID_SAR_ADC_SEL 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLKID_MALI_0_SEL 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLKID_MALI_0 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLKID_MALI_1_SEL 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLKID_MALI_1 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLKID_MALI 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLKID_CTS_AMCLK 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLKID_CTS_MCLK_I958 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLKID_CTS_I958 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLKID_32K_CLK 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLKID_SD_EMMC_A_CLK0 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLKID_SD_EMMC_B_CLK0 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLKID_SD_EMMC_C_CLK0 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLKID_VPU_0_SEL 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLKID_VPU_0 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLKID_VPU_1_SEL 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLKID_VPU_1 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLKID_VPU 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLKID_VAPB_0_SEL 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLKID_VAPB_0 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLKID_VAPB_1_SEL 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLKID_VAPB_1 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CLKID_VAPB_SEL 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLKID_VAPB 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLKID_VDEC_1 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLKID_VDEC_HEVC 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLKID_GEN_CLK 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLKID_VID_PLL 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CLKID_VCLK 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CLKID_VCLK2 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CLKID_VCLK_DIV1 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CLKID_VCLK_DIV2 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CLKID_VCLK_DIV4 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CLKID_VCLK_DIV6 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLKID_VCLK_DIV12 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLKID_VCLK2_DIV1 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLKID_VCLK2_DIV2 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLKID_VCLK2_DIV4 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CLKID_VCLK2_DIV6 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CLKID_VCLK2_DIV12 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CLKID_CTS_ENCI 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLKID_CTS_ENCP 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLKID_CTS_VDAC 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CLKID_HDMI_TX 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLKID_HDMI 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLKID_ACODEC 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #endif /* __GXBB_CLKC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags