^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ OR MIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Meson-G12A clock tree IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __G12A_CLKC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __G12A_CLKC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CLKID_SYS_PLL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CLKID_FIXED_PLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLKID_FCLK_DIV2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLKID_FCLK_DIV3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLKID_FCLK_DIV4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLKID_FCLK_DIV5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLKID_FCLK_DIV7 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLKID_GP0_PLL 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLKID_CLK81 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLKID_MPLL0 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLKID_MPLL1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLKID_MPLL2 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLKID_MPLL3 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLKID_DDR 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLKID_DOS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLKID_AUDIO_LOCKER 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLKID_MIPI_DSI_HOST 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLKID_ETH_PHY 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLKID_ISA 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLKID_PL301 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLKID_PERIPHS 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLKID_SPICC0 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLKID_I2C 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLKID_SANA 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLKID_SD 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLKID_RNG0 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLKID_UART0 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLKID_SPICC1 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLKID_HIU_IFACE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLKID_MIPI_DSI_PHY 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLKID_ASSIST_MISC 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLKID_SD_EMMC_A 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLKID_SD_EMMC_B 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLKID_SD_EMMC_C 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLKID_AUDIO_CODEC 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLKID_AUDIO 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLKID_ETH 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLKID_DEMUX 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLKID_AUDIO_IFIFO 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLKID_ADC 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLKID_UART1 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLKID_G2D 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLKID_RESET 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLKID_PCIE_COMB 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLKID_PARSER 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLKID_USB 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLKID_PCIE_PHY 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLKID_AHB_ARB0 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLKID_AHB_DATA_BUS 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLKID_AHB_CTRL_BUS 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLKID_HTX_HDCP22 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLKID_HTX_PCLK 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CLKID_BT656 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CLKID_USB1_DDR_BRIDGE 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CLKID_MMC_PCLK 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CLKID_UART2 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLKID_VPU_INTR 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CLKID_GIC 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CLKID_SD_EMMC_A_CLK0 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLKID_SD_EMMC_B_CLK0 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CLKID_SD_EMMC_C_CLK0 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLKID_HIFI_PLL 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CLKID_VCLK2_VENCI0 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CLKID_VCLK2_VENCI1 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CLKID_VCLK2_VENCP0 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CLKID_VCLK2_VENCP1 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CLKID_VCLK2_VENCT0 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CLKID_VCLK2_VENCT1 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CLKID_VCLK2_OTHER 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CLKID_VCLK2_ENCI 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CLKID_VCLK2_ENCP 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CLKID_DAC_CLK 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CLKID_AOCLK 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CLKID_IEC958 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CLKID_ENC480P 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CLKID_RNG1 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CLKID_VCLK2_ENCT 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CLKID_VCLK2_ENCL 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CLKID_VCLK2_VENCLMMC 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CLKID_VCLK2_VENCL 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CLKID_VCLK2_OTHER1 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CLKID_FCLK_DIV2P5 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CLKID_DMA 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CLKID_EFUSE 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CLKID_ROM_BOOT 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CLKID_RESET_SEC 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CLKID_SEC_AHB_APB3 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CLKID_VPU_0_SEL 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CLKID_VPU_0 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLKID_VPU_1_SEL 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLKID_VPU_1 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLKID_VPU 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLKID_VAPB_0_SEL 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLKID_VAPB_0 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLKID_VAPB_1_SEL 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLKID_VAPB_1 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLKID_VAPB_SEL 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLKID_VAPB 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLKID_HDMI_PLL 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLKID_VID_PLL 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLKID_VCLK 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLKID_VCLK2 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLKID_VCLK_DIV1 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLKID_VCLK_DIV2 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLKID_VCLK_DIV4 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLKID_VCLK_DIV6 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLKID_VCLK_DIV12 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLKID_VCLK2_DIV1 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLKID_VCLK2_DIV2 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLKID_VCLK2_DIV4 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLKID_VCLK2_DIV6 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLKID_VCLK2_DIV12 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLKID_CTS_ENCI 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLKID_CTS_ENCP 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLKID_CTS_VDAC 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CLKID_HDMI_TX 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLKID_HDMI 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLKID_MALI_0_SEL 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLKID_MALI_0 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLKID_MALI_1_SEL 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLKID_MALI_1 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CLKID_MALI 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CLKID_MPLL_50M 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CLKID_CPU_CLK 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CLKID_PCIE_PLL 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CLKID_VDEC_1 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CLKID_VDEC_HEVC 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLKID_VDEC_HEVCF 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLKID_TS 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLKID_CPUB_CLK 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLKID_GP1_PLL 243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CLKID_DSU_CLK 252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CLKID_CPU1_CLK 253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CLKID_CPU2_CLK 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLKID_CPU3_CLK 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLKID_SPICC0_SCLK 258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CLKID_SPICC1_SCLK 261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLKID_NNA_AXI_CLK 264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLKID_NNA_CORE_CLK 267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #endif /* __G12A_CLKC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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