Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define _DT_BINDINGS_CLOCK_EXYNOS7_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /* TOPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define DOUT_ACLK_PERIS			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define DOUT_SCLK_BUS0_PLL		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define DOUT_SCLK_BUS1_PLL		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define DOUT_SCLK_CC_PLL		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define DOUT_SCLK_MFC_PLL		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define DOUT_ACLK_CCORE_133		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define DOUT_ACLK_MSCL_532		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define ACLK_MSCL_532			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define DOUT_SCLK_AUD_PLL		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define FOUT_AUD_PLL			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define SCLK_AUD_PLL			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SCLK_MFC_PLL_B			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SCLK_MFC_PLL_A			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SCLK_BUS1_PLL_B			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SCLK_BUS1_PLL_A			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SCLK_BUS0_PLL_B			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SCLK_BUS0_PLL_A			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SCLK_CC_PLL_B			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SCLK_CC_PLL_A			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define ACLK_CCORE_133			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define ACLK_PERIS_66			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TOPC_NR_CLK			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /* TOP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DOUT_ACLK_PERIC1		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DOUT_ACLK_PERIC0		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CLK_SCLK_UART0			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CLK_SCLK_UART1			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CLK_SCLK_UART2			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CLK_SCLK_UART3			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CLK_SCLK_SPI0			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CLK_SCLK_SPI1			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CLK_SCLK_SPI2			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CLK_SCLK_SPI3			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CLK_SCLK_SPI4			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CLK_SCLK_SPDIF			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CLK_SCLK_PCM1			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CLK_SCLK_I2S1			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define CLK_ACLK_PERIC0_66		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CLK_ACLK_PERIC1_66		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define TOP0_NR_CLK			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /* TOP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define DOUT_ACLK_FSYS1_200		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define DOUT_ACLK_FSYS0_200		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define DOUT_SCLK_MMC2			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define DOUT_SCLK_MMC1			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define DOUT_SCLK_MMC0			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CLK_SCLK_MMC2			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CLK_SCLK_MMC1			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CLK_SCLK_MMC0			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CLK_ACLK_FSYS0_200		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define CLK_ACLK_FSYS1_200		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CLK_SCLK_PHY_FSYS1		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CLK_SCLK_PHY_FSYS1_26M		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define MOUT_SCLK_UFSUNIPRO20		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define DOUT_SCLK_UFSUNIPRO20		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define CLK_SCLK_UFSUNIPRO20		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define DOUT_SCLK_PHY_FSYS1		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define DOUT_SCLK_PHY_FSYS1_26M		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define TOP1_NR_CLK			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /* CCORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define PCLK_RTC			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define CCORE_NR_CLK			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /* PERIC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define PCLK_UART0			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define SCLK_UART0			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define PCLK_HSI2C0			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define PCLK_HSI2C1			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define PCLK_HSI2C4			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define PCLK_HSI2C5			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define PCLK_HSI2C9			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define PCLK_HSI2C10			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define PCLK_HSI2C11			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define PCLK_PWM			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define SCLK_PWM			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define PCLK_ADCIF			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define PERIC0_NR_CLK			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /* PERIC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define PCLK_UART1			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define PCLK_UART2			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define PCLK_UART3			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define SCLK_UART1			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define SCLK_UART2			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define SCLK_UART3			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define PCLK_HSI2C2			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PCLK_HSI2C3			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PCLK_HSI2C6			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PCLK_HSI2C7			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PCLK_HSI2C8			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PCLK_SPI0			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PCLK_SPI1			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PCLK_SPI2			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PCLK_SPI3			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PCLK_SPI4			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SCLK_SPI0			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SCLK_SPI1			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SCLK_SPI2			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SCLK_SPI3			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SCLK_SPI4			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PCLK_I2S1			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PCLK_PCM1			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PCLK_SPDIF			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SCLK_I2S1			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SCLK_PCM1			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SCLK_SPDIF			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PERIC1_NR_CLK			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* PERIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PCLK_CHIPID			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SCLK_CHIPID			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PCLK_WDT			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PCLK_TMU			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SCLK_TMU			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PERIS_NR_CLK			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* FSYS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ACLK_MMC2			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ACLK_AXIUS_USBDRD30X_FSYS0X	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ACLK_USBDRD300			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SCLK_USBDRD300_SUSPENDCLK	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SCLK_USBDRD300_REFCLK		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define OSCCLK_PHY_CLKOUT_USB30_PHY		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ACLK_PDMA0			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ACLK_PDMA1			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define FSYS0_NR_CLK			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* FSYS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ACLK_MMC1			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ACLK_MMC0			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PHYCLK_UFS20_TX0_SYMBOL		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PHYCLK_UFS20_RX0_SYMBOL		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PHYCLK_UFS20_RX1_SYMBOL		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ACLK_UFS20_LINK			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SCLK_UFSUNIPRO20_USER		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PHYCLK_UFS20_RX1_SYMBOL_USER	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PHYCLK_UFS20_RX0_SYMBOL_USER	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PHYCLK_UFS20_TX0_SYMBOL_USER	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SCLK_COMBO_PHY_EMBEDDED_26M	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DOUT_PCLK_FSYS1			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PCLK_GPIO_FSYS1			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MOUT_FSYS1_PHYCLK_SEL1		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define FSYS1_NR_CLK			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* MSCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define USERMUX_ACLK_MSCL_532		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DOUT_PCLK_MSCL			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ACLK_MSCL_0			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ACLK_MSCL_1			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ACLK_JPEG			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ACLK_G2D			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ACLK_LH_ASYNC_SI_MSCL_0		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ACLK_LH_ASYNC_SI_MSCL_1		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ACLK_AXI2ACEL_BRIDGE		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ACLK_XIU_MSCLX_0		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ACLK_XIU_MSCLX_1		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ACLK_QE_MSCL_0			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ACLK_QE_MSCL_1			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ACLK_QE_JPEG			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ACLK_QE_G2D			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define ACLK_PPMU_MSCL_0		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ACLK_PPMU_MSCL_1		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ACLK_MSCLNP_133			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ACLK_AHB2APB_MSCL0P		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define ACLK_AHB2APB_MSCL1P		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PCLK_MSCL_0			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PCLK_MSCL_1			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PCLK_JPEG			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PCLK_G2D			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PCLK_QE_MSCL_0			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PCLK_QE_MSCL_1			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PCLK_QE_JPEG			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PCLK_QE_G2D			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define PCLK_PPMU_MSCL_0		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PCLK_PPMU_MSCL_1		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define PCLK_AXI2ACEL_BRIDGE		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define PCLK_PMU_MSCL			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MSCL_NR_CLK			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* AUD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SCLK_I2S			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SCLK_PCM			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define PCLK_I2S			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define PCLK_PCM			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define ACLK_ADMA			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define AUD_NR_CLK			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */