^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Chanwoo Choi <cw00.choi@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_CLOCK_EXYNOS5433_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* CMU_TOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CLK_FOUT_ISP_PLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CLK_FOUT_AUD_PLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLK_MOUT_AUD_PLL 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_MOUT_ISP_PLL 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_MOUT_AUD_PLL_USER_T 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_MOUT_MPHY_PLL_USER 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_MOUT_MFC_PLL_USER 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_MOUT_BUS_PLL_USER 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_MOUT_ACLK_HEVC_400 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_MOUT_ACLK_CAM1_333 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_MOUT_ACLK_CAM1_552_B 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_MOUT_ACLK_CAM1_552_A 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_MOUT_ACLK_ISP_DIS_400 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_MOUT_ACLK_ISP_400 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_MOUT_ACLK_BUS0_400 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_MOUT_ACLK_MSCL_400_B 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_MOUT_ACLK_MSCL_400_A 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_MOUT_ACLK_GSCL_333 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_MOUT_ACLK_G2D_400_B 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_MOUT_ACLK_G2D_400_A 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_MOUT_SCLK_JPEG_C 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_MOUT_SCLK_JPEG_B 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_MOUT_SCLK_JPEG_A 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_MOUT_SCLK_MMC2_B 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_MOUT_SCLK_MMC2_A 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_MOUT_SCLK_MMC1_B 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_MOUT_SCLK_MMC1_A 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_MOUT_SCLK_MMC0_D 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_MOUT_SCLK_MMC0_C 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLK_MOUT_SCLK_MMC0_B 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLK_MOUT_SCLK_MMC0_A 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLK_MOUT_SCLK_SPI4 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLK_MOUT_SCLK_SPI3 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_MOUT_SCLK_UART2 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLK_MOUT_SCLK_UART1 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLK_MOUT_SCLK_UART0 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLK_MOUT_SCLK_SPI2 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLK_MOUT_SCLK_SPI1 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_MOUT_SCLK_SPI0 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLK_MOUT_ACLK_MFC_400_C 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_MOUT_ACLK_MFC_400_B 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLK_MOUT_ACLK_MFC_400_A 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLK_MOUT_SCLK_ISP_SENSOR2 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLK_MOUT_SCLK_ISP_SENSOR1 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLK_MOUT_SCLK_ISP_SENSOR0 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLK_MOUT_SCLK_ISP_UART 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLK_MOUT_SCLK_ISP_SPI1 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLK_MOUT_SCLK_ISP_SPI0 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLK_MOUT_SCLK_PCIE_100 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLK_MOUT_SCLK_UFSUNIPRO 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLK_MOUT_SCLK_USBHOST30 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CLK_MOUT_SCLK_USBDRD30 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CLK_MOUT_SCLK_SLIMBUS 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CLK_MOUT_SCLK_SPDIF 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CLK_MOUT_SCLK_AUDIO1 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLK_MOUT_SCLK_AUDIO0 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CLK_MOUT_SCLK_HDMI_SPDIF 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLK_DIV_ACLK_FSYS_200 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CLK_DIV_ACLK_IMEM_SSSX_266 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLK_DIV_ACLK_IMEM_200 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CLK_DIV_ACLK_IMEM_266 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CLK_DIV_ACLK_PERIC_66_B 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CLK_DIV_ACLK_PERIC_66_A 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CLK_DIV_ACLK_PERIS_66_B 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CLK_DIV_ACLK_PERIS_66_A 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CLK_DIV_SCLK_MMC1_B 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CLK_DIV_SCLK_MMC1_A 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CLK_DIV_SCLK_MMC0_B 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CLK_DIV_SCLK_MMC0_A 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CLK_DIV_SCLK_MMC2_B 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CLK_DIV_SCLK_MMC2_A 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CLK_DIV_SCLK_SPI1_B 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CLK_DIV_SCLK_SPI1_A 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CLK_DIV_SCLK_SPI0_B 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CLK_DIV_SCLK_SPI0_A 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CLK_DIV_SCLK_SPI2_B 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CLK_DIV_SCLK_SPI2_A 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CLK_DIV_SCLK_UART2 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CLK_DIV_SCLK_UART1 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CLK_DIV_SCLK_UART0 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CLK_DIV_SCLK_SPI4_B 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CLK_DIV_SCLK_SPI4_A 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CLK_DIV_SCLK_SPI3_B 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CLK_DIV_SCLK_SPI3_A 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CLK_DIV_SCLK_I2S1 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CLK_DIV_SCLK_PCM1 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CLK_DIV_SCLK_AUDIO1 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_DIV_SCLK_AUDIO0 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_DIV_ACLK_GSCL_111 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK_DIV_ACLK_GSCL_333 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_DIV_ACLK_HEVC_400 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_DIV_ACLK_MFC_400 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_DIV_ACLK_G2D_266 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_DIV_ACLK_G2D_400 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_DIV_ACLK_G3D_400 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_DIV_ACLK_BUS0_400 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_DIV_ACLK_BUS1_400 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_DIV_SCLK_PCIE_100 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_DIV_SCLK_USBHOST30 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLK_DIV_SCLK_UFSUNIPRO 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_DIV_SCLK_USBDRD30 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLK_DIV_SCLK_JPEG 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_DIV_ACLK_MSCL_400 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_DIV_ACLK_ISP_DIS_400 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_DIV_ACLK_ISP_400 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLK_DIV_ACLK_CAM0_333 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLK_DIV_ACLK_CAM0_400 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLK_DIV_ACLK_CAM0_552 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_DIV_ACLK_CAM1_333 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLK_DIV_ACLK_CAM1_400 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLK_DIV_ACLK_CAM1_552 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLK_DIV_SCLK_ISP_UART 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLK_DIV_SCLK_ISP_SPI1_B 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CLK_DIV_SCLK_ISP_SPI1_A 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLK_DIV_SCLK_ISP_SPI0_B 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLK_DIV_SCLK_ISP_SPI0_A 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLK_DIV_SCLK_ISP_SENSOR2_B 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLK_DIV_SCLK_ISP_SENSOR2_A 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLK_DIV_SCLK_ISP_SENSOR1_B 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CLK_DIV_SCLK_ISP_SENSOR1_A 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CLK_DIV_SCLK_ISP_SENSOR0_B 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CLK_DIV_SCLK_ISP_SENSOR0_A 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CLK_ACLK_PERIC_66 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CLK_ACLK_PERIS_66 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLK_ACLK_FSYS_200 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLK_SCLK_MMC2_FSYS 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLK_SCLK_MMC1_FSYS 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLK_SCLK_MMC0_FSYS 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CLK_SCLK_SPI4_PERIC 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CLK_SCLK_SPI3_PERIC 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CLK_SCLK_UART2_PERIC 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLK_SCLK_UART1_PERIC 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLK_SCLK_UART0_PERIC 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CLK_SCLK_SPI2_PERIC 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLK_SCLK_SPI1_PERIC 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLK_SCLK_SPI0_PERIC 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CLK_SCLK_SPDIF_PERIC 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CLK_SCLK_I2S1_PERIC 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CLK_SCLK_PCM1_PERIC 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CLK_SCLK_SLIMBUS 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CLK_SCLK_AUDIO1 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CLK_SCLK_AUDIO0 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLK_ACLK_G2D_266 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CLK_ACLK_G2D_400 221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CLK_ACLK_G3D_400 222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CLK_ACLK_IMEM_SSSX_266 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CLK_ACLK_BUS0_400 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CLK_ACLK_BUS1_400 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CLK_ACLK_IMEM_200 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CLK_ACLK_IMEM_266 227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CLK_SCLK_PCIE_100_FSYS 228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CLK_SCLK_UFSUNIPRO_FSYS 229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLK_SCLK_USBHOST30_FSYS 230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CLK_SCLK_USBDRD30_FSYS 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CLK_ACLK_GSCL_111 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CLK_ACLK_GSCL_333 233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CLK_SCLK_JPEG_MSCL 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CLK_ACLK_MSCL_400 235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CLK_ACLK_MFC_400 236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CLK_ACLK_HEVC_400 237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CLK_ACLK_ISP_DIS_400 238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CLK_ACLK_ISP_400 239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CLK_ACLK_CAM0_333 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CLK_ACLK_CAM0_400 241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CLK_ACLK_CAM0_552 242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CLK_ACLK_CAM1_333 243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CLK_ACLK_CAM1_400 244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CLK_ACLK_CAM1_552 245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CLK_SCLK_ISP_SENSOR2 246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CLK_SCLK_ISP_SENSOR1 247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CLK_SCLK_ISP_SENSOR0 248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CLK_SCLK_ISP_MCTADC_CAM1 249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CLK_SCLK_ISP_UART_CAM1 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CLK_SCLK_ISP_SPI1_CAM1 251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CLK_SCLK_ISP_SPI0_CAM1 252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CLK_SCLK_HDMI_SPDIF_DISP 253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TOP_NR_CLK 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* CMU_CPIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CLK_FOUT_MPHY_PLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CLK_MOUT_MPHY_PLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CLK_DIV_SCLK_MPHY 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CLK_SCLK_MPHY_PLL 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CLK_SCLK_UFS_MPHY 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CPIF_NR_CLK 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* CMU_MIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CLK_FOUT_MEM0_PLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CLK_FOUT_MEM1_PLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CLK_FOUT_BUS_PLL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CLK_FOUT_MFC_PLL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CLK_DOUT_MFC_PLL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CLK_DOUT_BUS_PLL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CLK_DOUT_MEM1_PLL 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CLK_DOUT_MEM0_PLL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CLK_MOUT_MFC_PLL_DIV2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CLK_MOUT_BUS_PLL_DIV2 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CLK_MOUT_MEM1_PLL_DIV2 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CLK_MOUT_MEM0_PLL_DIV2 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CLK_MOUT_MFC_PLL 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CLK_MOUT_BUS_PLL 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CLK_MOUT_MEM1_PLL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CLK_MOUT_MEM0_PLL 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CLK_MOUT_CLK2X_PHY_C 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CLK_MOUT_CLK2X_PHY_B 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CLK_MOUT_CLK2X_PHY_A 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CLK_MOUT_CLKM_PHY_C 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CLK_MOUT_CLKM_PHY_B 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CLK_MOUT_CLKM_PHY_A 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CLK_MOUT_ACLK_MIFNM_200 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CLK_MOUT_ACLK_MIFNM_400 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CLK_MOUT_ACLK_DISP_333_B 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CLK_MOUT_ACLK_DISP_333_A 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CLK_MOUT_SCLK_DECON_VCLK_C 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CLK_MOUT_SCLK_DECON_VCLK_B 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CLK_MOUT_SCLK_DECON_VCLK_A 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CLK_MOUT_SCLK_DECON_ECLK_C 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CLK_MOUT_SCLK_DECON_ECLK_B 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CLK_MOUT_SCLK_DECON_ECLK_A 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CLK_MOUT_SCLK_DSD_C 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CLK_MOUT_SCLK_DSD_B 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CLK_MOUT_SCLK_DSD_A 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CLK_MOUT_SCLK_DSIM0_C 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define CLK_MOUT_SCLK_DSIM0_B 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CLK_MOUT_SCLK_DSIM0_A 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CLK_MOUT_SCLK_DSIM1_C 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CLK_MOUT_SCLK_DSIM1_B 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define CLK_MOUT_SCLK_DSIM1_A 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CLK_DIV_SCLK_HPM_MIF 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CLK_DIV_ACLK_DREX1 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CLK_DIV_ACLK_DREX0 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CLK_DIV_CLK2XPHY 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CLK_DIV_ACLK_MIF_266 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CLK_DIV_ACLK_MIFND_133 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CLK_DIV_ACLK_MIF_133 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CLK_DIV_ACLK_MIFNM_200 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CLK_DIV_ACLK_MIF_200 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CLK_DIV_ACLK_MIF_400 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CLK_DIV_ACLK_BUS2_400 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define CLK_DIV_ACLK_DISP_333 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define CLK_DIV_ACLK_CPIF_200 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define CLK_DIV_SCLK_DSIM1 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CLK_DIV_SCLK_DECON_TV_VCLK 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CLK_DIV_SCLK_DSIM0 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CLK_DIV_SCLK_DSD 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CLK_DIV_SCLK_DECON_TV_ECLK 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CLK_DIV_SCLK_DECON_VCLK 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define CLK_DIV_SCLK_DECON_ECLK 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CLK_DIV_MIF_PRE 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CLK_CLK2X_PHY1 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CLK_CLK2X_PHY0 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CLK_CLKM_PHY1 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define CLK_CLKM_PHY0 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CLK_RCLK_DREX1 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define CLK_RCLK_DREX0 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CLK_ACLK_DREX1_TZ 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CLK_ACLK_DREX0_TZ 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CLK_ACLK_DREX1_PEREV 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define CLK_ACLK_DREX0_PEREV 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define CLK_ACLK_DREX1_MEMIF 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define CLK_ACLK_DREX0_MEMIF 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CLK_ACLK_DREX1_SCH 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define CLK_ACLK_DREX0_SCH 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define CLK_ACLK_DREX1_BUSIF 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CLK_ACLK_DREX0_BUSIF 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define CLK_ACLK_DREX1_BUSIF_RD 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define CLK_ACLK_DREX0_BUSIF_RD 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define CLK_ACLK_DREX1 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define CLK_ACLK_DREX0 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define CLK_ACLK_ASYNCAXIS_CP1 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define CLK_ACLK_ASYNCAXIM_CP1 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define CLK_ACLK_ASYNCAXIS_CP0 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define CLK_ACLK_ASYNCAXIM_CP0 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define CLK_ACLK_ASYNCAXIS_DREX1_3 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define CLK_ACLK_ASYNCAXIM_DREX1_3 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define CLK_ACLK_ASYNCAXIS_DREX1_1 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define CLK_ACLK_ASYNCAXIM_DREX1_1 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define CLK_ACLK_ASYNCAXIS_DREX1_0 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define CLK_ACLK_ASYNCAXIM_DREX1_0 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define CLK_ACLK_ASYNCAXIS_DREX0_3 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define CLK_ACLK_ASYNCAXIM_DREX0_3 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define CLK_ACLK_ASYNCAXIS_DREX0_1 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define CLK_ACLK_ASYNCAXIM_DREX0_1 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define CLK_ACLK_ASYNCAXIS_DREX0_0 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define CLK_ACLK_ASYNCAXIM_DREX0_0 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define CLK_ACLK_AHB2APB_MIF2P 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define CLK_ACLK_AHB2APB_MIF1P 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define CLK_ACLK_AHB2APB_MIF0P 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define CLK_ACLK_IXIU_CCI 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define CLK_ACLK_XIU_MIFSFRX 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define CLK_ACLK_MIFNP_133 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define CLK_ACLK_MIFNM_200 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define CLK_ACLK_MIFND_133 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define CLK_ACLK_MIFND_400 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define CLK_ACLK_CCI 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define CLK_ACLK_MIFND_266 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define CLK_ACLK_PPMU_DREX1S3 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define CLK_ACLK_PPMU_DREX1S1 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define CLK_ACLK_PPMU_DREX1S0 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define CLK_ACLK_PPMU_DREX0S3 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define CLK_ACLK_PPMU_DREX0S1 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define CLK_ACLK_PPMU_DREX0S0 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define CLK_ACLK_BTS_APOLLO 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define CLK_ACLK_BTS_ATLAS 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define CLK_ACLK_ACE_SEL_APOLL 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define CLK_ACLK_ACE_SEL_ATLAS 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define CLK_ACLK_AXIDS_CCI_MIFSFRX 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define CLK_ACLK_AXIUS_ATLAS_CCI 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define CLK_ACLK_AXISYNCDNS_CCI 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define CLK_ACLK_AXISYNCDN_CCI 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define CLK_ACLK_AXISYNCDN_NOC_D 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define CLK_ACLK_BUS2_400 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define CLK_ACLK_DISP_333 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define CLK_ACLK_CPIF_200 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define CLK_PCLK_PPMU_DREX1S3 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define CLK_PCLK_PPMU_DREX1S1 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define CLK_PCLK_PPMU_DREX1S0 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define CLK_PCLK_PPMU_DREX0S3 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define CLK_PCLK_PPMU_DREX0S1 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define CLK_PCLK_PPMU_DREX0S0 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define CLK_PCLK_BTS_APOLLO 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define CLK_PCLK_BTS_ATLAS 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define CLK_PCLK_ASYNCAXI_CP1 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define CLK_PCLK_ASYNCAXI_CP0 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define CLK_PCLK_ASYNCAXI_DREX1_3 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define CLK_PCLK_ASYNCAXI_DREX1_1 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define CLK_PCLK_ASYNCAXI_DREX1_0 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define CLK_PCLK_ASYNCAXI_DREX0_3 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define CLK_PCLK_ASYNCAXI_DREX0_1 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define CLK_PCLK_ASYNCAXI_DREX0_0 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define CLK_PCLK_MIFSRVND_133 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define CLK_PCLK_PMU_MIF 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define CLK_PCLK_SYSREG_MIF 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define CLK_PCLK_GPIO_ALIVE 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define CLK_PCLK_ABB 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define CLK_PCLK_PMU_APBIF 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define CLK_PCLK_DDR_PHY1 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define CLK_PCLK_DREX1 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define CLK_PCLK_DDR_PHY0 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define CLK_PCLK_DREX0 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define CLK_PCLK_DREX0_TZ 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define CLK_PCLK_DREX1_TZ 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define CLK_PCLK_MONOTONIC_CNT 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define CLK_PCLK_RTC 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define CLK_SCLK_DSIM1_DISP 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define CLK_SCLK_DECON_TV_VCLK_DISP 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define CLK_SCLK_FREQ_DET_BUS_PLL 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define CLK_SCLK_FREQ_DET_MFC_PLL 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define CLK_SCLK_FREQ_DET_MEM0_PLL 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define CLK_SCLK_FREQ_DET_MEM1_PLL 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define CLK_SCLK_DSIM0_DISP 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define CLK_SCLK_DSD_DISP 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define CLK_SCLK_DECON_TV_ECLK_DISP 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define CLK_SCLK_DECON_VCLK_DISP 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define CLK_SCLK_DECON_ECLK_DISP 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define CLK_SCLK_HPM_MIF 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define CLK_SCLK_MFC_PLL 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define CLK_SCLK_BUS_PLL 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define CLK_SCLK_BUS_PLL_APOLLO 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define CLK_SCLK_BUS_PLL_ATLAS 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define MIF_NR_CLK 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* CMU_PERIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define CLK_PCLK_SPI2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define CLK_PCLK_SPI1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define CLK_PCLK_SPI0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define CLK_PCLK_UART2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define CLK_PCLK_UART1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define CLK_PCLK_UART0 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define CLK_PCLK_HSI2C3 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define CLK_PCLK_HSI2C2 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define CLK_PCLK_HSI2C1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define CLK_PCLK_HSI2C0 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define CLK_PCLK_I2C7 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define CLK_PCLK_I2C6 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define CLK_PCLK_I2C5 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define CLK_PCLK_I2C4 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define CLK_PCLK_I2C3 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define CLK_PCLK_I2C2 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define CLK_PCLK_I2C1 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define CLK_PCLK_I2C0 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define CLK_PCLK_SPI4 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define CLK_PCLK_SPI3 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define CLK_PCLK_HSI2C11 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define CLK_PCLK_HSI2C10 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define CLK_PCLK_HSI2C9 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define CLK_PCLK_HSI2C8 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define CLK_PCLK_HSI2C7 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define CLK_PCLK_HSI2C6 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define CLK_PCLK_HSI2C5 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define CLK_PCLK_HSI2C4 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define CLK_SCLK_SPI4 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define CLK_SCLK_SPI3 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define CLK_SCLK_SPI2 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define CLK_SCLK_SPI1 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define CLK_SCLK_SPI0 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define CLK_SCLK_UART2 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define CLK_SCLK_UART1 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define CLK_SCLK_UART0 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define CLK_ACLK_AHB2APB_PERIC2P 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define CLK_ACLK_AHB2APB_PERIC1P 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define CLK_ACLK_AHB2APB_PERIC0P 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define CLK_ACLK_PERICNP_66 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define CLK_PCLK_SCI 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define CLK_PCLK_GPIO_FINGER 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define CLK_PCLK_GPIO_ESE 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define CLK_PCLK_PWM 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define CLK_PCLK_SPDIF 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define CLK_PCLK_PCM1 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define CLK_PCLK_I2S1 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define CLK_PCLK_ADCIF 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define CLK_PCLK_GPIO_TOUCH 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define CLK_PCLK_GPIO_NFC 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define CLK_PCLK_GPIO_PERIC 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define CLK_PCLK_PMU_PERIC 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define CLK_PCLK_SYSREG_PERIC 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define CLK_SCLK_IOCLK_SPI4 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define CLK_SCLK_IOCLK_SPI3 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define CLK_SCLK_SCI 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define CLK_SCLK_SC_IN 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define CLK_SCLK_PWM 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define CLK_SCLK_IOCLK_SPI2 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define CLK_SCLK_IOCLK_SPI1 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define CLK_SCLK_IOCLK_SPI0 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define CLK_SCLK_IOCLK_I2S1_BCLK 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define CLK_SCLK_SPDIF 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define CLK_SCLK_PCM1 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define CLK_SCLK_I2S1 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define CLK_DIV_SCLK_SCI 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define CLK_DIV_SCLK_SC_IN 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define PERIC_NR_CLK 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* CMU_PERIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define CLK_PCLK_HPM_APBIF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define CLK_PCLK_TMU1_APBIF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define CLK_PCLK_TMU0_APBIF 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define CLK_PCLK_PMU_PERIS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define CLK_PCLK_SYSREG_PERIS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define CLK_PCLK_CMU_TOP_APBIF 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define CLK_PCLK_WDT_APOLLO 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define CLK_PCLK_WDT_ATLAS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define CLK_PCLK_MCT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define CLK_PCLK_HDMI_CEC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define CLK_ACLK_AHB2APB_PERIS1P 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define CLK_ACLK_AHB2APB_PERIS0P 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define CLK_ACLK_PERISNP_66 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define CLK_PCLK_TZPC12 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define CLK_PCLK_TZPC11 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define CLK_PCLK_TZPC10 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define CLK_PCLK_TZPC9 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define CLK_PCLK_TZPC8 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define CLK_PCLK_TZPC7 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define CLK_PCLK_TZPC6 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define CLK_PCLK_TZPC5 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define CLK_PCLK_TZPC4 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define CLK_PCLK_TZPC3 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define CLK_PCLK_TZPC2 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define CLK_PCLK_TZPC1 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define CLK_PCLK_TZPC0 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define CLK_PCLK_SECKEY_APBIF 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define CLK_PCLK_CHIPID_APBIF 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define CLK_PCLK_TOPRTC 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define CLK_PCLK_CUSTOM_EFUSE_APBIF 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define CLK_PCLK_ANTIRBK_CNT_APBIF 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define CLK_PCLK_OTP_CON_APBIF 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define CLK_SCLK_ASV_TB 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define CLK_SCLK_TMU1 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define CLK_SCLK_TMU0 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define CLK_SCLK_SECKEY 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define CLK_SCLK_CHIPID 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define CLK_SCLK_TOPRTC 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define CLK_SCLK_CUSTOM_EFUSE 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define CLK_SCLK_ANTIRBK_CNT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define CLK_SCLK_OTP_CON 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define PERIS_NR_CLK 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* CMU_FSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define CLK_MOUT_ACLK_FSYS_200_USER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define CLK_MOUT_SCLK_MMC2_USER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define CLK_MOUT_SCLK_MMC1_USER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define CLK_MOUT_SCLK_MMC0_USER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define CLK_MOUT_SCLK_UFS_MPHY_USER 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define CLK_MOUT_SCLK_PCIE_100_USER 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define CLK_MOUT_SCLK_UFSUNIPRO_USER 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define CLK_MOUT_SCLK_USBHOST30_USER 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define CLK_MOUT_SCLK_USBDRD30_USER 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define CLK_MOUT_SCLK_MPHY 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define CLK_ACLK_PCIE 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define CLK_ACLK_PDMA1 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define CLK_ACLK_TSI 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define CLK_ACLK_MMC2 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define CLK_ACLK_MMC1 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define CLK_ACLK_MMC0 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define CLK_ACLK_UFS 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define CLK_ACLK_USBHOST20 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define CLK_ACLK_USBHOST30 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define CLK_ACLK_USBDRD30 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define CLK_ACLK_PDMA0 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define CLK_SCLK_MMC2 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define CLK_SCLK_MMC1 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define CLK_SCLK_MMC0 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define CLK_PDMA1 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define CLK_PDMA0 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define CLK_ACLK_XIU_FSYSPX 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define CLK_ACLK_AHB_USBLINKH1 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define CLK_ACLK_SMMU_PDMA1 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define CLK_ACLK_BTS_PCIE 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define CLK_ACLK_AXIUS_PDMA1 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define CLK_ACLK_SMMU_PDMA0 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define CLK_ACLK_BTS_UFS 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define CLK_ACLK_BTS_USBHOST30 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define CLK_ACLK_BTS_USBDRD30 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define CLK_ACLK_AXIUS_PDMA0 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define CLK_ACLK_AXIUS_USBHS 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define CLK_ACLK_AXIUS_FSYSSX 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define CLK_ACLK_AHB2APB_FSYSP 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define CLK_ACLK_AHB2AXI_USBHS 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define CLK_ACLK_AHB_USBLINKH0 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define CLK_ACLK_AHB_USBHS 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define CLK_ACLK_AHB_FSYSH 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define CLK_ACLK_XIU_FSYSX 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define CLK_ACLK_XIU_FSYSSX 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define CLK_ACLK_FSYSNP_200 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define CLK_ACLK_FSYSND_200 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define CLK_PCLK_PCIE_CTRL 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define CLK_PCLK_SMMU_PDMA1 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define CLK_PCLK_PCIE_PHY 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define CLK_PCLK_BTS_PCIE 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define CLK_PCLK_SMMU_PDMA0 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define CLK_PCLK_BTS_UFS 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define CLK_PCLK_BTS_USBHOST30 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define CLK_PCLK_BTS_USBDRD30 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define CLK_PCLK_GPIO_FSYS 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define CLK_PCLK_PMU_FSYS 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define CLK_PCLK_SYSREG_FSYS 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define CLK_SCLK_PCIE_100 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define CLK_PHYCLK_UFS_RX1_SYMBOL 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define CLK_PHYCLK_UFS_RX0_SYMBOL 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define CLK_PHYCLK_UFS_TX1_SYMBOL 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define CLK_PHYCLK_UFS_TX0_SYMBOL 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define CLK_PHYCLK_USBHOST20_PHY_HSIC1 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define CLK_PHYCLK_USBHOST20_PHY_FREECLK 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define CLK_SCLK_MPHY 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define CLK_SCLK_UFSUNIPRO 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define CLK_SCLK_USBHOST30 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define CLK_SCLK_USBDRD30 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define CLK_PCIE 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define FSYS_NR_CLK 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* CMU_G2D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define CLK_MUX_ACLK_G2D_266_USER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define CLK_MUX_ACLK_G2D_400_USER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define CLK_DIV_PCLK_G2D 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define CLK_ACLK_SMMU_MDMA1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define CLK_ACLK_BTS_MDMA1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define CLK_ACLK_BTS_G2D 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define CLK_ACLK_ALB_G2D 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define CLK_ACLK_AXIUS_G2DX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define CLK_ACLK_ASYNCAXI_SYSX 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define CLK_ACLK_AHB2APB_G2D1P 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define CLK_ACLK_AHB2APB_G2D0P 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define CLK_ACLK_XIU_G2DX 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define CLK_ACLK_G2DNP_133 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define CLK_ACLK_G2DND_400 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define CLK_ACLK_MDMA1 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define CLK_ACLK_G2D 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define CLK_ACLK_SMMU_G2D 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define CLK_PCLK_SMMU_MDMA1 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define CLK_PCLK_BTS_MDMA1 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define CLK_PCLK_BTS_G2D 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define CLK_PCLK_ALB_G2D 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define CLK_PCLK_ASYNCAXI_SYSX 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define CLK_PCLK_PMU_G2D 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define CLK_PCLK_SYSREG_G2D 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define CLK_PCLK_G2D 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define CLK_PCLK_SMMU_G2D 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define G2D_NR_CLK 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* CMU_DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define CLK_FOUT_DISP_PLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define CLK_MOUT_DISP_PLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define CLK_MOUT_SCLK_DSIM1_USER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define CLK_MOUT_SCLK_DSIM0_USER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define CLK_MOUT_SCLK_DSD_USER 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define CLK_MOUT_SCLK_DECON_TV_ECLK_USER 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define CLK_MOUT_SCLK_DECON_VCLK_USER 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define CLK_MOUT_SCLK_DECON_ECLK_USER 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define CLK_MOUT_SCLK_DECON_TV_VCLK_USER 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define CLK_MOUT_ACLK_DISP_333_USER 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define CLK_MOUT_SCLK_DSIM0 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define CLK_MOUT_SCLK_DECON_TV_ECLK 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define CLK_MOUT_SCLK_DECON_VCLK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define CLK_MOUT_SCLK_DECON_ECLK 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define CLK_MOUT_SCLK_DSIM1_B_DISP 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define CLK_MOUT_SCLK_DSIM1_A_DISP 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define CLK_DIV_SCLK_DSIM1_DISP 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define CLK_DIV_SCLK_DECON_TV_VCLK_DISP 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define CLK_DIV_SCLK_DSIM0_DISP 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define CLK_DIV_SCLK_DECON_TV_ECLK_DISP 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define CLK_DIV_SCLK_DECON_VCLK_DISP 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define CLK_DIV_SCLK_DECON_ECLK_DISP 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define CLK_DIV_PCLK_DISP 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define CLK_ACLK_DECON_TV 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define CLK_ACLK_DECON 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define CLK_ACLK_SMMU_TV1X 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define CLK_ACLK_SMMU_TV0X 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define CLK_ACLK_SMMU_DECON1X 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define CLK_ACLK_SMMU_DECON0X 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define CLK_ACLK_BTS_DECON_TV_M3 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define CLK_ACLK_BTS_DECON_TV_M2 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define CLK_ACLK_BTS_DECON_TV_M1 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define CLK_ACLK_BTS_DECON_TV_M0 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define CLK_ACLK_BTS_DECON_NM4 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define CLK_ACLK_BTS_DECON_NM3 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define CLK_ACLK_BTS_DECON_NM2 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define CLK_ACLK_BTS_DECON_NM1 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define CLK_ACLK_BTS_DECON_NM0 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define CLK_ACLK_AHB2APB_DISPSFR2P 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define CLK_ACLK_AHB2APB_DISPSFR1P 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define CLK_ACLK_AHB2APB_DISPSFR0P 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define CLK_ACLK_AHB_DISPH 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define CLK_ACLK_XIU_TV1X 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define CLK_ACLK_XIU_TV0X 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define CLK_ACLK_XIU_DECON1X 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define CLK_ACLK_XIU_DECON0X 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define CLK_ACLK_XIU_DISP1X 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define CLK_ACLK_XIU_DISPNP_100 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define CLK_ACLK_DISP1ND_333 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define CLK_ACLK_DISP0ND_333 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define CLK_PCLK_SMMU_TV1X 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define CLK_PCLK_SMMU_TV0X 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define CLK_PCLK_SMMU_DECON1X 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define CLK_PCLK_SMMU_DECON0X 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define CLK_PCLK_BTS_DECON_TV_M3 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define CLK_PCLK_BTS_DECON_TV_M2 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define CLK_PCLK_BTS_DECON_TV_M1 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define CLK_PCLK_BTS_DECON_TV_M0 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define CLK_PCLK_BTS_DECONM4 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define CLK_PCLK_BTS_DECONM3 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define CLK_PCLK_BTS_DECONM2 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define CLK_PCLK_BTS_DECONM1 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define CLK_PCLK_BTS_DECONM0 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define CLK_PCLK_MIC1 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define CLK_PCLK_PMU_DISP 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define CLK_PCLK_SYSREG_DISP 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define CLK_PCLK_HDMIPHY 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define CLK_PCLK_HDMI 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define CLK_PCLK_MIC0 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define CLK_PCLK_DSIM1 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define CLK_PCLK_DSIM0 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define CLK_PCLK_DECON_TV 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define CLK_SCLK_DSIM1 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define CLK_SCLK_DECON_TV_VCLK 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define CLK_PHYCLK_HDMI_PIXEL 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define CLK_SCLK_RGB_VCLK_TO_SMIES 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define CLK_SCLK_FREQ_DET_DISP_PLL 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define CLK_SCLK_RGB_VCLK_TO_DSIM0 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define CLK_SCLK_RGB_VCLK_TO_MIC0 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define CLK_SCLK_DSD 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define CLK_SCLK_HDMI_SPDIF 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define CLK_SCLK_DSIM0 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define CLK_SCLK_DECON_TV_ECLK 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define CLK_SCLK_DECON_VCLK 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define CLK_SCLK_DECON_ECLK 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define CLK_SCLK_RGB_VCLK 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define CLK_SCLK_RGB_TV_VCLK 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define CLK_PCLK_DECON 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define DISP_NR_CLK 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* CMU_AUD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define CLK_MOUT_AUD_PLL_USER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define CLK_MOUT_SCLK_AUD_PCM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define CLK_MOUT_SCLK_AUD_I2S 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define CLK_DIV_ATCLK_AUD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define CLK_DIV_PCLK_DBG_AUD 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define CLK_DIV_ACLK_AUD 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define CLK_DIV_AUD_CA5 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define CLK_DIV_SCLK_AUD_SLIMBUS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define CLK_DIV_SCLK_AUD_UART 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define CLK_DIV_SCLK_AUD_PCM 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define CLK_DIV_SCLK_AUD_I2S 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define CLK_ACLK_INTR_CTRL 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define CLK_ACLK_AXIDS2_LPASSP 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define CLK_ACLK_AXIDS1_LPASSP 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define CLK_ACLK_AXI2APB1_LPASSP 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define CLK_ACLK_AXI2APH_LPASSP 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define CLK_ACLK_SMMU_LPASSX 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define CLK_ACLK_AXIDS0_LPASSP 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define CLK_ACLK_AXI2APB0_LPASSP 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define CLK_ACLK_XIU_LPASSX 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define CLK_ACLK_AUDNP_133 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define CLK_ACLK_AUDND_133 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define CLK_ACLK_SRAMC 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define CLK_ACLK_DMAC 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define CLK_PCLK_WDT1 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define CLK_PCLK_WDT0 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define CLK_PCLK_SFR1 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define CLK_PCLK_SMMU_LPASSX 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define CLK_PCLK_GPIO_AUD 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define CLK_PCLK_PMU_AUD 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define CLK_PCLK_SYSREG_AUD 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define CLK_PCLK_AUD_SLIMBUS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define CLK_PCLK_AUD_UART 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define CLK_PCLK_AUD_PCM 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define CLK_PCLK_AUD_I2S 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define CLK_PCLK_TIMER 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define CLK_PCLK_SFR0_CTRL 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define CLK_ATCLK_AUD 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define CLK_PCLK_DBG_AUD 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define CLK_SCLK_AUD_CA5 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define CLK_SCLK_JTAG_TCK 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define CLK_SCLK_SLIMBUS_CLKIN 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define CLK_SCLK_AUD_SLIMBUS 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define CLK_SCLK_AUD_UART 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define CLK_SCLK_AUD_PCM 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define CLK_SCLK_I2S_BCLK 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define CLK_SCLK_AUD_I2S 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define AUD_NR_CLK 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* CMU_BUS{0|1|2} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define CLK_DIV_PCLK_BUS_133 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define CLK_ACLK_AHB2APB_BUSP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define CLK_ACLK_BUSNP_133 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define CLK_ACLK_BUSND_400 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define CLK_PCLK_BUSSRVND_133 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define CLK_PCLK_PMU_BUS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define CLK_PCLK_SYSREG_BUS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define CLK_MOUT_ACLK_BUS2_400_USER 8 /* Only CMU_BUS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define BUSx_NR_CLK 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* CMU_G3D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define CLK_FOUT_G3D_PLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define CLK_MOUT_ACLK_G3D_400 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define CLK_MOUT_G3D_PLL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define CLK_DIV_SCLK_HPM_G3D 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define CLK_DIV_PCLK_G3D 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define CLK_DIV_ACLK_G3D 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define CLK_ACLK_BTS_G3D1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define CLK_ACLK_BTS_G3D0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define CLK_ACLK_ASYNCAPBS_G3D 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define CLK_ACLK_ASYNCAPBM_G3D 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define CLK_ACLK_AHB2APB_G3DP 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define CLK_ACLK_G3DNP_150 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define CLK_ACLK_G3DND_600 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define CLK_ACLK_G3D 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define CLK_PCLK_BTS_G3D1 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define CLK_PCLK_BTS_G3D0 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define CLK_PCLK_PMU_G3D 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define CLK_PCLK_SYSREG_G3D 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define CLK_SCLK_HPM_G3D 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define G3D_NR_CLK 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* CMU_GSCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define CLK_MOUT_ACLK_GSCL_111_USER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define CLK_MOUT_ACLK_GSCL_333_USER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define CLK_ACLK_BTS_GSCL2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define CLK_ACLK_BTS_GSCL1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define CLK_ACLK_BTS_GSCL0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define CLK_ACLK_AHB2APB_GSCLP 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define CLK_ACLK_XIU_GSCLX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define CLK_ACLK_GSCLNP_111 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define CLK_ACLK_GSCLRTND_333 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define CLK_ACLK_GSCLBEND_333 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define CLK_ACLK_GSD 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define CLK_ACLK_GSCL2 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define CLK_ACLK_GSCL1 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define CLK_ACLK_GSCL0 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define CLK_ACLK_SMMU_GSCL0 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define CLK_ACLK_SMMU_GSCL1 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define CLK_ACLK_SMMU_GSCL2 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define CLK_PCLK_BTS_GSCL2 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define CLK_PCLK_BTS_GSCL1 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define CLK_PCLK_BTS_GSCL0 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define CLK_PCLK_PMU_GSCL 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define CLK_PCLK_SYSREG_GSCL 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define CLK_PCLK_GSCL2 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define CLK_PCLK_GSCL1 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define CLK_PCLK_GSCL0 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define CLK_PCLK_SMMU_GSCL0 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define CLK_PCLK_SMMU_GSCL1 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define CLK_PCLK_SMMU_GSCL2 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define GSCL_NR_CLK 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /* CMU_APOLLO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define CLK_FOUT_APOLLO_PLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define CLK_MOUT_APOLLO_PLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define CLK_MOUT_BUS_PLL_APOLLO_USER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define CLK_MOUT_APOLLO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define CLK_DIV_CNTCLK_APOLLO 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define CLK_DIV_PCLK_DBG_APOLLO 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define CLK_DIV_ATCLK_APOLLO 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define CLK_DIV_PCLK_APOLLO 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define CLK_DIV_ACLK_APOLLO 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define CLK_DIV_APOLLO2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define CLK_DIV_APOLLO1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define CLK_DIV_SCLK_HPM_APOLLO 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define CLK_DIV_APOLLO_PLL 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define CLK_ACLK_ATBDS_APOLLO_3 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define CLK_ACLK_ATBDS_APOLLO_2 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define CLK_ACLK_ATBDS_APOLLO_1 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define CLK_ACLK_ATBDS_APOLLO_0 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define CLK_ACLK_ASYNCACES_APOLLO_CCI 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define CLK_ACLK_AHB2APB_APOLLOP 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define CLK_ACLK_APOLLONP_200 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define CLK_PCLK_ASAPBMST_CSSYS_APOLLO 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define CLK_PCLK_PMU_APOLLO 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define CLK_PCLK_SYSREG_APOLLO 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define CLK_CNTCLK_APOLLO 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define CLK_SCLK_HPM_APOLLO 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define CLK_SCLK_APOLLO 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define APOLLO_NR_CLK 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /* CMU_ATLAS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define CLK_FOUT_ATLAS_PLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define CLK_MOUT_ATLAS_PLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define CLK_MOUT_BUS_PLL_ATLAS_USER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define CLK_MOUT_ATLAS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define CLK_DIV_CNTCLK_ATLAS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define CLK_DIV_PCLK_DBG_ATLAS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define CLK_DIV_ATCLK_ATLASO 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define CLK_DIV_PCLK_ATLAS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define CLK_DIV_ACLK_ATLAS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define CLK_DIV_ATLAS2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define CLK_DIV_ATLAS1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define CLK_DIV_SCLK_HPM_ATLAS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define CLK_DIV_ATLAS_PLL 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define CLK_ACLK_ATB_AUD_CSSYS 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define CLK_ACLK_ATB_APOLLO3_CSSYS 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define CLK_ACLK_ATB_APOLLO2_CSSYS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define CLK_ACLK_ATB_APOLLO1_CSSYS 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define CLK_ACLK_ATB_APOLLO0_CSSYS 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define CLK_ACLK_ASYNCAHBS_CSSYS_SSS 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define CLK_ACLK_ASYNCACES_ATLAS_CCI 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define CLK_ACLK_AHB2APB_ATLASP 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define CLK_ACLK_ATLASNP_200 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define CLK_PCLK_ASYNCAPB_AUD_CSSYS 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define CLK_PCLK_ASYNCAPB_ISP_CSSYS 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define CLK_PCLK_PMU_ATLAS 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define CLK_PCLK_SYSREG_ATLAS 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define CLK_PCLK_SECJTAG 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define CLK_CNTCLK_ATLAS 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define CLK_SCLK_FREQ_DET_ATLAS_PLL 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define CLK_SCLK_HPM_ATLAS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define CLK_TRACECLK 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #define CLK_CTMCLK 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define CLK_HCLK_CSSYS 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define CLK_PCLK_DBG_CSSYS 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define CLK_PCLK_DBG 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define CLK_ATCLK 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #define CLK_SCLK_ATLAS 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define ATLAS_NR_CLK 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /* CMU_MSCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define CLK_MOUT_SCLK_JPEG_USER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define CLK_MOUT_ACLK_MSCL_400_USER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define CLK_MOUT_SCLK_JPEG 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define CLK_DIV_PCLK_MSCL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define CLK_ACLK_BTS_JPEG 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define CLK_ACLK_BTS_M2MSCALER1 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define CLK_ACLK_BTS_M2MSCALER0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define CLK_ACLK_AHB2APB_MSCL0P 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define CLK_ACLK_XIU_MSCLX 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define CLK_ACLK_MSCLNP_100 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define CLK_ACLK_MSCLND_400 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define CLK_ACLK_JPEG 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define CLK_ACLK_M2MSCALER1 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define CLK_ACLK_M2MSCALER0 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define CLK_ACLK_SMMU_M2MSCALER0 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define CLK_ACLK_SMMU_M2MSCALER1 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define CLK_ACLK_SMMU_JPEG 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define CLK_PCLK_BTS_JPEG 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define CLK_PCLK_BTS_M2MSCALER1 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define CLK_PCLK_BTS_M2MSCALER0 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define CLK_PCLK_PMU_MSCL 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define CLK_PCLK_SYSREG_MSCL 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define CLK_PCLK_JPEG 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define CLK_PCLK_M2MSCALER1 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define CLK_PCLK_M2MSCALER0 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define CLK_PCLK_SMMU_M2MSCALER0 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define CLK_PCLK_SMMU_M2MSCALER1 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define CLK_PCLK_SMMU_JPEG 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define CLK_SCLK_JPEG 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define MSCL_NR_CLK 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /* CMU_MFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define CLK_MOUT_ACLK_MFC_400_USER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define CLK_DIV_PCLK_MFC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define CLK_ACLK_BTS_MFC_1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define CLK_ACLK_BTS_MFC_0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define CLK_ACLK_AHB2APB_MFCP 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define CLK_ACLK_XIU_MFCX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define CLK_ACLK_MFCNP_100 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define CLK_ACLK_MFCND_400 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define CLK_ACLK_MFC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define CLK_ACLK_SMMU_MFC_1 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define CLK_ACLK_SMMU_MFC_0 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define CLK_PCLK_BTS_MFC_1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define CLK_PCLK_BTS_MFC_0 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define CLK_PCLK_PMU_MFC 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define CLK_PCLK_SYSREG_MFC 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define CLK_PCLK_MFC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define CLK_PCLK_SMMU_MFC_1 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define CLK_PCLK_SMMU_MFC_0 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define MFC_NR_CLK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /* CMU_HEVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define CLK_MOUT_ACLK_HEVC_400_USER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define CLK_DIV_PCLK_HEVC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define CLK_ACLK_BTS_HEVC_1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define CLK_ACLK_BTS_HEVC_0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define CLK_ACLK_AHB2APB_HEVCP 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define CLK_ACLK_XIU_HEVCX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define CLK_ACLK_HEVCNP_100 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define CLK_ACLK_HEVCND_400 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define CLK_ACLK_HEVC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #define CLK_ACLK_SMMU_HEVC_1 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define CLK_ACLK_SMMU_HEVC_0 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define CLK_PCLK_BTS_HEVC_1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define CLK_PCLK_BTS_HEVC_0 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #define CLK_PCLK_PMU_HEVC 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define CLK_PCLK_SYSREG_HEVC 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define CLK_PCLK_HEVC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define CLK_PCLK_SMMU_HEVC_1 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define CLK_PCLK_SMMU_HEVC_0 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define HEVC_NR_CLK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /* CMU_ISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #define CLK_MOUT_ACLK_ISP_DIS_400_USER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define CLK_MOUT_ACLK_ISP_400_USER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define CLK_DIV_PCLK_ISP_DIS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #define CLK_DIV_PCLK_ISP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define CLK_DIV_ACLK_ISP_D_200 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define CLK_DIV_ACLK_ISP_C_200 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define CLK_ACLK_ISP_D_GLUE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define CLK_ACLK_SCALERP 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define CLK_ACLK_3DNR 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define CLK_ACLK_DIS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define CLK_ACLK_SCALERC 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define CLK_ACLK_DRC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #define CLK_ACLK_ISP 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define CLK_ACLK_AXIUS_SCALERP 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define CLK_ACLK_AXIUS_SCALERC 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define CLK_ACLK_AXIUS_DRC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define CLK_ACLK_ASYNCAHBM_ISP2P 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #define CLK_ACLK_ASYNCAHBM_ISP1P 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #define CLK_ACLK_ASYNCAXIS_DIS1 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define CLK_ACLK_ASYNCAXIS_DIS0 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define CLK_ACLK_ASYNCAXIM_DIS1 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) #define CLK_ACLK_ASYNCAXIM_DIS0 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define CLK_ACLK_ASYNCAXIM_ISP2P 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) #define CLK_ACLK_ASYNCAXIM_ISP1P 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define CLK_ACLK_AHB2APB_ISP2P 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #define CLK_ACLK_AHB2APB_ISP1P 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define CLK_ACLK_AXI2APB_ISP2P 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #define CLK_ACLK_AXI2APB_ISP1P 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define CLK_ACLK_XIU_ISPEX1 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define CLK_ACLK_XIU_ISPEX0 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define CLK_ACLK_ISPND_400 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #define CLK_ACLK_SMMU_SCALERP 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define CLK_ACLK_SMMU_3DNR 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #define CLK_ACLK_SMMU_DIS1 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #define CLK_ACLK_SMMU_DIS0 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #define CLK_ACLK_SMMU_SCALERC 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define CLK_ACLK_SMMU_DRC 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #define CLK_ACLK_SMMU_ISP 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #define CLK_ACLK_BTS_SCALERP 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define CLK_ACLK_BTS_3DR 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define CLK_ACLK_BTS_DIS1 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define CLK_ACLK_BTS_DIS0 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define CLK_ACLK_BTS_SCALERC 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #define CLK_ACLK_BTS_DRC 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define CLK_ACLK_BTS_ISP 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define CLK_PCLK_SMMU_SCALERP 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) #define CLK_PCLK_SMMU_3DNR 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define CLK_PCLK_SMMU_DIS1 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) #define CLK_PCLK_SMMU_DIS0 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define CLK_PCLK_SMMU_SCALERC 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #define CLK_PCLK_SMMU_DRC 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define CLK_PCLK_SMMU_ISP 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #define CLK_PCLK_BTS_SCALERP 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) #define CLK_PCLK_BTS_3DNR 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define CLK_PCLK_BTS_DIS1 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define CLK_PCLK_BTS_DIS0 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define CLK_PCLK_BTS_SCALERC 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define CLK_PCLK_BTS_DRC 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) #define CLK_PCLK_BTS_ISP 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) #define CLK_PCLK_ASYNCAXI_DIS1 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #define CLK_PCLK_ASYNCAXI_DIS0 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #define CLK_PCLK_PMU_ISP 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define CLK_PCLK_SYSREG_ISP 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #define CLK_PCLK_CMU_ISP_LOCAL 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define CLK_PCLK_SCALERP 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define CLK_PCLK_3DNR 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #define CLK_PCLK_DIS_CORE 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #define CLK_PCLK_DIS 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define CLK_PCLK_SCALERC 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #define CLK_PCLK_DRC 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define CLK_PCLK_ISP 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #define CLK_SCLK_PIXELASYNCS_DIS 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #define CLK_SCLK_PIXELASYNCM_DIS 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define CLK_SCLK_PIXELASYNCS_SCALERP 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) #define CLK_SCLK_PIXELASYNCM_ISPD 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #define CLK_SCLK_PIXELASYNCS_ISPC 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define CLK_SCLK_PIXELASYNCM_ISPC 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #define ISP_NR_CLK 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /* CMU_CAM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #define CLK_MOUT_ACLK_CAM0_333_USER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define CLK_MOUT_ACLK_CAM0_400_USER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define CLK_MOUT_ACLK_CAM0_552_USER 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define CLK_MOUT_ACLK_LITE_D_B 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define CLK_MOUT_ACLK_LITE_D_A 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define CLK_MOUT_ACLK_LITE_B_B 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define CLK_MOUT_ACLK_LITE_B_A 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) #define CLK_MOUT_ACLK_LITE_A_B 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define CLK_MOUT_ACLK_LITE_A_A 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define CLK_MOUT_ACLK_CAM0_400 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define CLK_MOUT_ACLK_CSIS1_B 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define CLK_MOUT_ACLK_CSIS1_A 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #define CLK_MOUT_ACLK_CSIS0_B 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define CLK_MOUT_ACLK_CSIS0_A 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define CLK_MOUT_ACLK_3AA1_B 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define CLK_MOUT_ACLK_3AA1_A 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define CLK_MOUT_ACLK_3AA0_B 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define CLK_MOUT_ACLK_3AA0_A 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define CLK_MOUT_SCLK_LITE_FREECNT_C 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define CLK_MOUT_SCLK_LITE_FREECNT_B 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define CLK_MOUT_SCLK_LITE_FREECNT_A 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define CLK_DIV_PCLK_CAM0_50 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define CLK_DIV_ACLK_CAM0_200 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define CLK_DIV_ACLK_CAM0_BUS_400 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define CLK_DIV_PCLK_LITE_D 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define CLK_DIV_ACLK_LITE_D 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define CLK_DIV_PCLK_LITE_B 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define CLK_DIV_ACLK_LITE_B 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define CLK_DIV_PCLK_LITE_A 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define CLK_DIV_ACLK_LITE_A 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define CLK_DIV_ACLK_CSIS1 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define CLK_DIV_ACLK_CSIS0 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define CLK_DIV_PCLK_3AA1 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define CLK_DIV_ACLK_3AA1 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define CLK_DIV_PCLK_3AA0 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define CLK_DIV_ACLK_3AA0 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define CLK_DIV_SCLK_PIXELASYNC_LITE_C 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define CLK_DIV_PCLK_PIXELASYNC_LITE_C 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #define CLK_ACLK_CSIS1 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #define CLK_ACLK_CSIS0 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #define CLK_ACLK_3AA1 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define CLK_ACLK_3AA0 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define CLK_ACLK_LITE_D 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define CLK_ACLK_LITE_B 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define CLK_ACLK_LITE_A 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define CLK_ACLK_AHBSYNCDN 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #define CLK_ACLK_AXIUS_LITE_D 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define CLK_ACLK_AXIUS_LITE_B 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define CLK_ACLK_AXIUS_LITE_A 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #define CLK_ACLK_ASYNCAPBM_3AA1 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define CLK_ACLK_ASYNCAPBS_3AA1 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) #define CLK_ACLK_ASYNCAPBM_3AA0 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #define CLK_ACLK_ASYNCAPBS_3AA0 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #define CLK_ACLK_ASYNCAPBM_LITE_D 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #define CLK_ACLK_ASYNCAPBS_LITE_D 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #define CLK_ACLK_ASYNCAPBM_LITE_B 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #define CLK_ACLK_ASYNCAPBS_LITE_B 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #define CLK_ACLK_ASYNCAPBM_LITE_A 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) #define CLK_ACLK_ASYNCAPBS_LITE_A 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #define CLK_ACLK_ASYNCAXIM_ISP0P 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) #define CLK_ACLK_ASYNCAXIM_3AA1 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #define CLK_ACLK_ASYNCAXIS_3AA1 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #define CLK_ACLK_ASYNCAXIM_3AA0 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #define CLK_ACLK_ASYNCAXIS_3AA0 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define CLK_ACLK_ASYNCAXIM_LITE_D 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define CLK_ACLK_ASYNCAXIS_LITE_D 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #define CLK_ACLK_ASYNCAXIM_LITE_B 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #define CLK_ACLK_ASYNCAXIS_LITE_B 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #define CLK_ACLK_ASYNCAXIM_LITE_A 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #define CLK_ACLK_ASYNCAXIS_LITE_A 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define CLK_ACLK_AHB2APB_ISPSFRP 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define CLK_ACLK_AXI2APB_ISP0P 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #define CLK_ACLK_AXI2AHB_ISP0P 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #define CLK_ACLK_XIU_IS0X 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define CLK_ACLK_XIU_ISP0EX 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define CLK_ACLK_CAM0NP_276 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) #define CLK_ACLK_CAM0ND_400 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define CLK_ACLK_SMMU_3AA1 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define CLK_ACLK_SMMU_3AA0 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #define CLK_ACLK_SMMU_LITE_D 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define CLK_ACLK_SMMU_LITE_B 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define CLK_ACLK_SMMU_LITE_A 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #define CLK_ACLK_BTS_3AA1 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define CLK_ACLK_BTS_3AA0 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define CLK_ACLK_BTS_LITE_D 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define CLK_ACLK_BTS_LITE_B 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define CLK_ACLK_BTS_LITE_A 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define CLK_PCLK_SMMU_3AA1 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define CLK_PCLK_SMMU_3AA0 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define CLK_PCLK_SMMU_LITE_D 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define CLK_PCLK_SMMU_LITE_B 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define CLK_PCLK_SMMU_LITE_A 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #define CLK_PCLK_BTS_3AA1 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #define CLK_PCLK_BTS_3AA0 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define CLK_PCLK_BTS_LITE_D 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #define CLK_PCLK_BTS_LITE_B 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #define CLK_PCLK_BTS_LITE_A 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #define CLK_PCLK_ASYNCAXI_CAM1 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #define CLK_PCLK_ASYNCAXI_3AA1 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #define CLK_PCLK_ASYNCAXI_3AA0 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #define CLK_PCLK_ASYNCAXI_LITE_D 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #define CLK_PCLK_ASYNCAXI_LITE_B 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) #define CLK_PCLK_ASYNCAXI_LITE_A 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define CLK_PCLK_PMU_CAM0 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #define CLK_PCLK_SYSREG_CAM0 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define CLK_PCLK_CMU_CAM0_LOCAL 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define CLK_PCLK_CSIS1 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #define CLK_PCLK_CSIS0 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #define CLK_PCLK_3AA1 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #define CLK_PCLK_3AA0 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #define CLK_PCLK_LITE_D 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #define CLK_PCLK_LITE_B 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define CLK_PCLK_LITE_A 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #define CLK_PHYCLK_RXBYTECLKHS0_S4 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define CLK_PHYCLK_RXBYTECLKHS0_S2A 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #define CLK_SCLK_LITE_FREECNT 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #define CLK_SCLK_PIXELASYNCM_3AA1 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #define CLK_SCLK_PIXELASYNCM_3AA0 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define CLK_SCLK_PIXELASYNCS_3AA0 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #define CLK_SCLK_PIXELASYNCM_LITE_C 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #define CLK_SCLK_PIXELASYNCM_LITE_C_INIT 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #define CLK_SCLK_PIXELASYNCS_LITE_C_INIT 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define CAM0_NR_CLK 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /* CMU_CAM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define CLK_PHYCLK_RXBYTEECLKHS0_S2B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define CLK_MOUT_SCLK_ISP_UART_USER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define CLK_MOUT_SCLK_ISP_SPI1_USER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define CLK_MOUT_SCLK_ISP_SPI0_USER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define CLK_MOUT_ACLK_CAM1_333_USER 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) #define CLK_MOUT_ACLK_CAM1_400_USER 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #define CLK_MOUT_ACLK_CAM1_552_USER 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define CLK_MOUT_ACLK_CSIS2_B 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define CLK_MOUT_ACLK_CSIS2_A 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define CLK_MOUT_ACLK_FD_B 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #define CLK_MOUT_ACLK_FD_A 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #define CLK_MOUT_ACLK_LITE_C_B 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #define CLK_MOUT_ACLK_LITE_C_A 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) #define CLK_DIV_SCLK_ISP_MPWM 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #define CLK_DIV_PCLK_CAM1_83 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) #define CLK_DIV_PCLK_CAM1_166 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #define CLK_DIV_PCLK_DBG_CAM1 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #define CLK_DIV_ATCLK_CAM1 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define CLK_DIV_ACLK_CSIS2 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define CLK_DIV_PCLK_FD 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #define CLK_DIV_ACLK_FD 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define CLK_DIV_PCLK_LITE_C 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #define CLK_DIV_ACLK_LITE_C 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) #define CLK_ACLK_ISP_GIC 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) #define CLK_ACLK_FD 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define CLK_ACLK_LITE_C 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define CLK_ACLK_CSIS2 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define CLK_ACLK_ASYNCAPBM_FD 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #define CLK_ACLK_ASYNCAPBS_FD 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define CLK_ACLK_ASYNCAPBM_LITE_C 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define CLK_ACLK_ASYNCAPBS_LITE_C 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define CLK_ACLK_ASYNCAHBS_SFRISP2H2 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define CLK_ACLK_ASYNCAHBS_SFRISP2H1 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) #define CLK_ACLK_ASYNCAXIM_CA5 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #define CLK_ACLK_ASYNCAXIS_CA5 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #define CLK_ACLK_ASYNCAXIS_ISPX2 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) #define CLK_ACLK_ASYNCAXIS_ISPX1 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) #define CLK_ACLK_ASYNCAXIS_ISPX0 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define CLK_ACLK_ASYNCAXIM_ISPEX 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) #define CLK_ACLK_ASYNCAXIM_ISP3P 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #define CLK_ACLK_ASYNCAXIS_ISP3P 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) #define CLK_ACLK_ASYNCAXIM_FD 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #define CLK_ACLK_ASYNCAXIS_FD 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) #define CLK_ACLK_ASYNCAXIM_LITE_C 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) #define CLK_ACLK_ASYNCAXIS_LITE_C 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) #define CLK_ACLK_AHB2APB_ISP5P 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) #define CLK_ACLK_AHB2APB_ISP3P 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) #define CLK_ACLK_AXI2APB_ISP3P 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) #define CLK_ACLK_AHB_SFRISP2H 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) #define CLK_ACLK_AXI_ISP_HX_R 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) #define CLK_ACLK_AXI_ISP_CX_R 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) #define CLK_ACLK_AXI_ISP_HX 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #define CLK_ACLK_AXI_ISP_CX 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #define CLK_ACLK_XIU_ISPX 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) #define CLK_ACLK_XIU_ISPEX 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) #define CLK_ACLK_CAM1NP_333 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #define CLK_ACLK_CAM1ND_400 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) #define CLK_ACLK_SMMU_ISPCPU 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) #define CLK_ACLK_SMMU_FD 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) #define CLK_ACLK_SMMU_LITE_C 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) #define CLK_ACLK_BTS_ISP3P 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) #define CLK_ACLK_BTS_FD 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #define CLK_ACLK_BTS_LITE_C 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) #define CLK_ACLK_AHBDN_SFRISP2H 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) #define CLK_ACLK_AHBDN_ISP5P 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #define CLK_ACLK_AXIUS_ISP3P 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #define CLK_ACLK_AXIUS_FD 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #define CLK_ACLK_AXIUS_LITE_C 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #define CLK_PCLK_SMMU_ISPCPU 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #define CLK_PCLK_SMMU_FD 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) #define CLK_PCLK_SMMU_LITE_C 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) #define CLK_PCLK_BTS_ISP3P 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) #define CLK_PCLK_BTS_FD 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) #define CLK_PCLK_BTS_LITE_C 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #define CLK_PCLK_ASYNCAXIM_CA5 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) #define CLK_PCLK_ASYNCAXIM_ISPEX 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) #define CLK_PCLK_ASYNCAXIM_ISP3P 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) #define CLK_PCLK_ASYNCAXIM_FD 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) #define CLK_PCLK_ASYNCAXIM_LITE_C 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) #define CLK_PCLK_PMU_CAM1 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) #define CLK_PCLK_SYSREG_CAM1 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) #define CLK_PCLK_CMU_CAM1_LOCAL 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #define CLK_PCLK_ISP_MCTADC 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) #define CLK_PCLK_ISP_WDT 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) #define CLK_PCLK_ISP_PWM 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) #define CLK_PCLK_ISP_UART 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #define CLK_PCLK_ISP_MCUCTL 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) #define CLK_PCLK_ISP_SPI1 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #define CLK_PCLK_ISP_SPI0 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) #define CLK_PCLK_ISP_I2C2 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) #define CLK_PCLK_ISP_I2C1 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #define CLK_PCLK_ISP_I2C0 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) #define CLK_PCLK_ISP_MPWM 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) #define CLK_PCLK_FD 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #define CLK_PCLK_LITE_C 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) #define CLK_PCLK_CSIS2 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) #define CLK_SCLK_ISP_I2C2 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) #define CLK_SCLK_ISP_I2C1 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) #define CLK_SCLK_ISP_I2C0 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) #define CLK_SCLK_ISP_PWM 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) #define CLK_PHYCLK_RXBYTECLKHS0_S2B 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #define CLK_SCLK_LITE_C_FREECNT 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) #define CLK_SCLK_PIXELASYNCM_FD 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) #define CLK_SCLK_ISP_MCTADC 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) #define CLK_SCLK_ISP_UART 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) #define CLK_SCLK_ISP_SPI1 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #define CLK_SCLK_ISP_SPI0 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #define CLK_SCLK_ISP_MPWM 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) #define CLK_PCLK_DBG_ISP 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) #define CLK_ATCLK_ISP 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) #define CLK_SCLK_ISP_CA5 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #define CAM1_NR_CLK 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) /* CMU_IMEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) #define CLK_ACLK_SLIMSSS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) #define CLK_PCLK_SLIMSSS 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) #define IMEM_NR_CLK 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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