^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Andrzej Hajda <a.hajda@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Device Tree binding constants for Exynos5420 clock controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _DT_BINDINGS_CLOCK_EXYNOS_5420_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* core clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLK_FIN_PLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLK_FOUT_APLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_FOUT_CPLL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_FOUT_DPLL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_FOUT_EPLL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_FOUT_RPLL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_FOUT_IPLL 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_FOUT_SPLL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_FOUT_VPLL 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_FOUT_MPLL 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_FOUT_BPLL 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_FOUT_KPLL 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_ARM_CLK 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_KFC_CLK 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* gate for special clocks (sclk) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_SCLK_UART0 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_SCLK_UART1 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_SCLK_UART2 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_SCLK_UART3 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_SCLK_MMC0 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_SCLK_MMC1 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_SCLK_MMC2 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_SCLK_SPI0 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_SCLK_SPI1 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_SCLK_SPI2 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_SCLK_I2S1 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_SCLK_I2S2 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLK_SCLK_PCM1 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLK_SCLK_PCM2 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLK_SCLK_SPDIF 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLK_SCLK_HDMI 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_SCLK_PIXEL 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLK_SCLK_DP1 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLK_SCLK_MIPI1 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLK_SCLK_FIMD1 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLK_SCLK_MAUDIO0 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_SCLK_MAUPCM0 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLK_SCLK_USBD300 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_SCLK_USBD301 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLK_SCLK_USBPHY300 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLK_SCLK_USBPHY301 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLK_SCLK_UNIPRO 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLK_SCLK_PWM 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLK_SCLK_GSCL_WA 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLK_SCLK_GSCL_WB 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLK_SCLK_HDMIPHY 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLK_MAU_EPLL 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLK_SCLK_HSIC_12M 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLK_SCLK_MPHY_IXTAL24 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CLK_SCLK_BPLL 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* gate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CLK_UART0 257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLK_UART1 258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CLK_UART2 259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CLK_UART3 260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLK_I2C0 261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CLK_I2C1 262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLK_I2C2 263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CLK_I2C3 264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CLK_USI0 265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CLK_USI1 266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CLK_USI2 267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CLK_USI3 268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CLK_I2C_HDMI 269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CLK_TSADC 270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CLK_SPI0 271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CLK_SPI1 272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CLK_SPI2 273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CLK_KEYIF 274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CLK_I2S1 275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CLK_I2S2 276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CLK_PCM1 277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CLK_PCM2 278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CLK_PWM 279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CLK_SPDIF 280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CLK_USI4 281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CLK_USI5 282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CLK_USI6 283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CLK_ACLK66_PSGEN 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CLK_CHIPID 301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CLK_SYSREG 302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CLK_TZPC0 303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CLK_TZPC1 304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CLK_TZPC2 305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CLK_TZPC3 306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_TZPC4 307
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_TZPC5 308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK_TZPC6 309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_TZPC7 310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_TZPC8 311
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_TZPC9 312
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_HDMI_CEC 313
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_SECKEY 314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_MCT 315
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_WDT 316
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_RTC 317
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_TMU 318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLK_TMU_GPU 319
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_PCLK66_GPIO 330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLK_ACLK200_FSYS2 350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_MMC0 351
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_MMC1 352
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_MMC2 353
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLK_SROMC 354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLK_UFS 355
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLK_ACLK200_FSYS 360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_TSI 361
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLK_PDMA0 362
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLK_PDMA1 363
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLK_RTIC 364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLK_USBH20 365
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CLK_USBD300 366
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLK_USBD301 367
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLK_ACLK400_MSCL 380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLK_MSCL0 381
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLK_MSCL1 382
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLK_MSCL2 383
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CLK_SMMU_MSCL0 384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CLK_SMMU_MSCL1 385
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CLK_SMMU_MSCL2 386
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CLK_ACLK333 400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CLK_MFC 401
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CLK_SMMU_MFCL 402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLK_SMMU_MFCR 403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLK_ACLK200_DISP1 410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLK_DSIM1 411
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLK_DP1 412
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CLK_HDMI 413
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CLK_ACLK300_DISP1 420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CLK_FIMD1 421
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLK_SMMU_FIMD1M0 422
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLK_SMMU_FIMD1M1 423
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CLK_ACLK166 430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLK_MIXER 431
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLK_ACLK266 440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CLK_ROTATOR 441
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CLK_MDMA1 442
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CLK_SMMU_ROTATOR 443
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CLK_SMMU_MDMA1 444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CLK_ACLK300_JPEG 450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CLK_JPEG 451
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLK_JPEG2 452
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CLK_SMMU_JPEG 453
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CLK_SMMU_JPEG2 454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CLK_ACLK300_GSCL 460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CLK_SMMU_GSCL0 461
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CLK_SMMU_GSCL1 462
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CLK_GSCL_WA 463
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CLK_GSCL_WB 464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CLK_GSCL0 465
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CLK_GSCL1 466
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLK_FIMC_3AA 467
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CLK_ACLK266_G2D 470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CLK_SSS 471
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CLK_SLIM_SSS 472
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CLK_MDMA0 473
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CLK_ACLK333_G2D 480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CLK_G2D 481
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CLK_ACLK333_432_GSCL 490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CLK_SMMU_3AA 491
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CLK_SMMU_FIMCL0 492
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CLK_SMMU_FIMCL1 493
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CLK_SMMU_FIMCL3 494
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CLK_FIMC_LITE3 495
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CLK_FIMC_LITE0 496
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CLK_FIMC_LITE1 497
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CLK_ACLK_G3D 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CLK_G3D 501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CLK_SMMU_MIXER 502
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CLK_SMMU_G2D 503
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CLK_SMMU_MDMA0 504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CLK_MC 505
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CLK_TOP_RTC 506
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CLK_SCLK_UART_ISP 510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CLK_SCLK_SPI0_ISP 511
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CLK_SCLK_SPI1_ISP 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CLK_SCLK_PWM_ISP 513
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CLK_SCLK_ISP_SENSOR0 514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CLK_SCLK_ISP_SENSOR1 515
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CLK_SCLK_ISP_SENSOR2 516
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CLK_ACLK432_SCALER 517
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CLK_ACLK432_CAM 518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CLK_ACLK_FL1550_CAM 519
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CLK_ACLK550_CAM 520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CLK_CLKM_PHY0 521
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CLK_CLKM_PHY1 522
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CLK_ACLK_PPMU_DREX0_0 523
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CLK_ACLK_PPMU_DREX0_1 524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CLK_ACLK_PPMU_DREX1_0 525
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CLK_ACLK_PPMU_DREX1_1 526
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CLK_PCLK_PPMU_DREX0_0 527
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CLK_PCLK_PPMU_DREX0_1 528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CLK_PCLK_PPMU_DREX1_0 529
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CLK_PCLK_PPMU_DREX1_1 530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* mux clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CLK_MOUT_HDMI 640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CLK_MOUT_G3D 641
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CLK_MOUT_VPLL 642
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CLK_MOUT_MAUDIO0 643
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CLK_MOUT_USER_ACLK333 644
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CLK_MOUT_SW_ACLK333 645
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CLK_MOUT_USER_ACLK200_DISP1 646
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CLK_MOUT_SW_ACLK200 647
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CLK_MOUT_USER_ACLK300_DISP1 648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CLK_MOUT_SW_ACLK300 649
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CLK_MOUT_USER_ACLK400_DISP1 650
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CLK_MOUT_SW_ACLK400 651
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CLK_MOUT_USER_ACLK300_GSCL 652
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CLK_MOUT_SW_ACLK300_GSCL 653
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CLK_MOUT_MCLK_CDREX 654
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CLK_MOUT_BPLL 655
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CLK_MOUT_MX_MSPLL_CCORE 656
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CLK_MOUT_EPLL 657
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CLK_MOUT_MAU_EPLL 658
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CLK_MOUT_USER_MAU_EPLL 659
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CLK_MOUT_SCLK_SPLL 660
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CLK_MOUT_MX_MSPLL_CCORE_PHY 661
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CLK_MOUT_SW_ACLK_G3D 662
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CLK_MOUT_APLL 663
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CLK_MOUT_MSPLL_CPU 664
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CLK_MOUT_KPLL 665
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CLK_MOUT_MSPLL_KFC 666
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* divider clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CLK_DOUT_PIXEL 768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CLK_DOUT_ACLK400_WCORE 769
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CLK_DOUT_ACLK400_ISP 770
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CLK_DOUT_ACLK400_MSCL 771
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CLK_DOUT_ACLK200 772
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define CLK_DOUT_ACLK200_FSYS2 773
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CLK_DOUT_ACLK100_NOC 774
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define CLK_DOUT_PCLK200_FSYS 775
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CLK_DOUT_ACLK200_FSYS 776
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define CLK_DOUT_ACLK333_432_GSCL 777
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CLK_DOUT_ACLK333_432_ISP 778
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CLK_DOUT_ACLK66 779
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define CLK_DOUT_ACLK333_432_ISP0 780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define CLK_DOUT_ACLK266 781
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CLK_DOUT_ACLK166 782
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CLK_DOUT_ACLK333 783
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CLK_DOUT_ACLK333_G2D 784
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CLK_DOUT_ACLK266_G2D 785
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CLK_DOUT_ACLK_G3D 786
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CLK_DOUT_ACLK300_JPEG 787
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CLK_DOUT_ACLK300_DISP1 788
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CLK_DOUT_ACLK300_GSCL 789
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CLK_DOUT_ACLK400_DISP1 790
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CLK_DOUT_PCLK_CDREX 791
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CLK_DOUT_SCLK_CDREX 792
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define CLK_DOUT_ACLK_CDREX1 793
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define CLK_DOUT_CCLK_DREX0 794
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define CLK_DOUT_CLK2X_PHY0 795
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CLK_DOUT_PCLK_CORE_MEM 796
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CLK_FF_DOUT_SPLL2 797
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CLK_DOUT_PCLK_DREX0 798
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CLK_DOUT_PCLK_DREX1 799
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* must be greater than maximal clock id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CLK_NR_CLKS 800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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