Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (c) 2016 Krzysztof Kozlowski
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Device Tree binding constants for Exynos5421 clock controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* core clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLK_FIN_PLL		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLK_FOUT_APLL		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_FOUT_CPLL		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_FOUT_MPLL		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_FOUT_BPLL		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_FOUT_KPLL		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_FOUT_EPLL		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* gate for special clocks (sclk) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_SCLK_UART0		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_SCLK_UART1		129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_SCLK_UART2		130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_SCLK_UART3		131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_SCLK_MMC0		132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_SCLK_MMC1		133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_SCLK_MMC2		134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_SCLK_USBD300	150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_SCLK_USBD301	151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_SCLK_USBPHY300	152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_SCLK_USBPHY301	153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_SCLK_PWM		155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* gate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_UART0		257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_UART1		258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_UART2		259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_UART3		260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_I2C0		261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLK_I2C1		262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLK_I2C2		263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLK_I2C3		264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLK_USI0		265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_USI1		266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLK_USI2		267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLK_USI3		268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLK_TSADC		270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLK_PWM			279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_MCT			315
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLK_WDT			316
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_RTC			317
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLK_TMU			318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLK_MMC0		351
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLK_MMC1		352
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLK_MMC2		353
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLK_PDMA0		362
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLK_PDMA1		363
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLK_USBH20		365
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLK_USBD300		366
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLK_USBD301		367
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLK_SSS			471
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CLK_NR_CLKS		512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */