Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Andrzej Hajda <a.hajda@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Device Tree binding constants for Exynos5250 clock controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define _DT_BINDINGS_CLOCK_EXYNOS_5250_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) /* core clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define CLK_FIN_PLL		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define CLK_FOUT_APLL		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define CLK_FOUT_MPLL		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define CLK_FOUT_BPLL		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define CLK_FOUT_GPLL		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define CLK_FOUT_CPLL		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CLK_FOUT_EPLL		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define CLK_FOUT_VPLL		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CLK_ARM_CLK		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* gate for special clocks (sclk) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CLK_SCLK_CAM_BAYER	128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CLK_SCLK_CAM0		129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CLK_SCLK_CAM1		130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CLK_SCLK_GSCL_WA	131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CLK_SCLK_GSCL_WB	132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CLK_SCLK_FIMD1		133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CLK_SCLK_MIPI1		134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CLK_SCLK_DP		135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CLK_SCLK_HDMI		136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CLK_SCLK_PIXEL		137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CLK_SCLK_AUDIO0		138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CLK_SCLK_MMC0		139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CLK_SCLK_MMC1		140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CLK_SCLK_MMC2		141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CLK_SCLK_MMC3		142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CLK_SCLK_SATA		143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CLK_SCLK_USB3		144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CLK_SCLK_JPEG		145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CLK_SCLK_UART0		146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CLK_SCLK_UART1		147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CLK_SCLK_UART2		148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CLK_SCLK_UART3		149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CLK_SCLK_PWM		150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CLK_SCLK_AUDIO1		151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CLK_SCLK_AUDIO2		152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define CLK_SCLK_SPDIF		153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CLK_SCLK_SPI0		154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CLK_SCLK_SPI1		155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CLK_SCLK_SPI2		156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CLK_DIV_I2S1		157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define CLK_DIV_I2S2		158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define CLK_SCLK_HDMIPHY	159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CLK_DIV_PCM0		160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /* gate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CLK_GSCL0		256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CLK_GSCL1		257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CLK_GSCL2		258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CLK_GSCL3		259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define CLK_GSCL_WA		260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CLK_GSCL_WB		261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CLK_SMMU_GSCL0		262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CLK_SMMU_GSCL1		263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define CLK_SMMU_GSCL2		264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define CLK_SMMU_GSCL3		265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CLK_MFC			266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define CLK_SMMU_MFCL		267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define CLK_SMMU_MFCR		268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define CLK_ROTATOR		269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CLK_JPEG		270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define CLK_MDMA1		271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define CLK_SMMU_ROTATOR	272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define CLK_SMMU_JPEG		273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define CLK_SMMU_MDMA1		274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define CLK_PDMA0		275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define CLK_PDMA1		276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define CLK_SATA		277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define CLK_USBOTG		278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define CLK_MIPI_HSI		279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define CLK_SDMMC0		280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define CLK_SDMMC1		281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define CLK_SDMMC2		282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define CLK_SDMMC3		283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define CLK_SROMC		284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CLK_USB2		285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CLK_USB3		286
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CLK_SATA_PHYCTRL	287
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CLK_SATA_PHYI2C		288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define CLK_UART0		289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define CLK_UART1		290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define CLK_UART2		291
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define CLK_UART3		292
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define CLK_UART4		293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define CLK_I2C0		294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define CLK_I2C1		295
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define CLK_I2C2		296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_I2C3		297
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_I2C4		298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK_I2C5		299
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_I2C6		300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_I2C7		301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_I2C_HDMI		302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_ADC			303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_SPI0		304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_SPI1		305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_SPI2		306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_I2S1		307
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_I2S2		308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLK_PCM1		309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_PCM2		310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLK_PWM			311
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_SPDIF		312
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_AC97		313
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_HSI2C0		314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLK_HSI2C1		315
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLK_HSI2C2		316
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLK_HSI2C3		317
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_CHIPID		318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLK_SYSREG		319
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLK_PMU			320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLK_CMU_TOP		321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLK_CMU_CORE		322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CLK_CMU_MEM		323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLK_TZPC0		324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLK_TZPC1		325
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLK_TZPC2		326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLK_TZPC3		327
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLK_TZPC4		328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CLK_TZPC5		329
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CLK_TZPC6		330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CLK_TZPC7		331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CLK_TZPC8		332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CLK_TZPC9		333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CLK_HDMI_CEC		334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLK_MCT			335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLK_WDT			336
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLK_RTC			337
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLK_TMU			338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CLK_FIMD1		339
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CLK_MIE1		340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CLK_DSIM0		341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLK_DP			342
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLK_MIXER		343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CLK_HDMI		344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLK_G2D			345
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLK_MDMA0		346
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CLK_SMMU_MDMA0		347
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CLK_SSS			348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CLK_G3D			349
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CLK_SMMU_TV		350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CLK_SMMU_FIMD1		351
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CLK_SMMU_2D		352
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLK_SMMU_FIMC_ISP	353
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CLK_SMMU_FIMC_DRC	354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CLK_SMMU_FIMC_SCC	355
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CLK_SMMU_FIMC_SCP	356
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CLK_SMMU_FIMC_FD	357
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CLK_SMMU_FIMC_MCU	358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CLK_SMMU_FIMC_ODC	359
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CLK_SMMU_FIMC_DIS0	360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CLK_SMMU_FIMC_DIS1	361
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CLK_SMMU_FIMC_3DNR	362
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLK_SMMU_FIMC_LITE0	363
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CLK_SMMU_FIMC_LITE1	364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CLK_CAMIF_TOP		365
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* mux clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CLK_MOUT_HDMI		1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CLK_MOUT_GPLL		1025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CLK_MOUT_ACLK200_DISP1_SUB	1026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CLK_MOUT_ACLK300_DISP1_SUB	1027
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CLK_MOUT_APLL		1028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CLK_MOUT_MPLL		1029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* must be greater than maximal clock id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CLK_NR_CLKS		1030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */