Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * 	Author: Tomasz Figa <t.figa@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Device Tree binding constants for Samsung Exynos3250 clock controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Let each exported clock get a unique index, which is used on DT-enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * platforms to lookup the clock from a clock specifier. These indices are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * therefore considered an ABI and so must not be changed. This implies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * that new clocks should be added either in free spaces between clock groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * or at the end.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * Main CMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CLK_OSCSEL			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CLK_FIN_PLL			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CLK_FOUT_APLL			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CLK_FOUT_VPLL			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CLK_FOUT_UPLL			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CLK_FOUT_MPLL			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CLK_ARM_CLK			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* Muxes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CLK_MOUT_MPLL_USER_L		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CLK_MOUT_GDL			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CLK_MOUT_MPLL_USER_R		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CLK_MOUT_GDR			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CLK_MOUT_EBI			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CLK_MOUT_ACLK_200		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CLK_MOUT_ACLK_160		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CLK_MOUT_ACLK_100		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CLK_MOUT_ACLK_266_1		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CLK_MOUT_ACLK_266_0		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CLK_MOUT_ACLK_266		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CLK_MOUT_VPLL			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CLK_MOUT_EPLL_USER		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CLK_MOUT_EBI_1			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CLK_MOUT_UPLL			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define CLK_MOUT_ACLK_400_MCUISP_SUB	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CLK_MOUT_MPLL			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CLK_MOUT_ACLK_400_MCUISP	33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CLK_MOUT_VPLLSRC		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CLK_MOUT_CAM1			35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define CLK_MOUT_CAM_BLK		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define CLK_MOUT_MFC			37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CLK_MOUT_MFC_1			38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define CLK_MOUT_MFC_0			39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define CLK_MOUT_G3D			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CLK_MOUT_G3D_1			41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CLK_MOUT_G3D_0			42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CLK_MOUT_MIPI0			43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CLK_MOUT_FIMD0			44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define CLK_MOUT_UART_ISP		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CLK_MOUT_SPI1_ISP		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CLK_MOUT_SPI0_ISP		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CLK_MOUT_TSADC			48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define CLK_MOUT_MMC1			49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define CLK_MOUT_MMC0			50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CLK_MOUT_UART1			51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define CLK_MOUT_UART0			52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define CLK_MOUT_SPI1			53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define CLK_MOUT_SPI0			54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CLK_MOUT_AUDIO			55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define CLK_MOUT_MPLL_USER_C		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define CLK_MOUT_HPM			57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define CLK_MOUT_CORE			58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define CLK_MOUT_APLL			59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define CLK_MOUT_ACLK_266_SUB		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define CLK_MOUT_UART2			61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define CLK_MOUT_MMC2			62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) /* Dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define CLK_DIV_GPL			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define CLK_DIV_GDL			65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define CLK_DIV_GPR			66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define CLK_DIV_GDR			67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define CLK_DIV_MPLL_PRE		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CLK_DIV_ACLK_400_MCUISP		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CLK_DIV_EBI			70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CLK_DIV_ACLK_200		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CLK_DIV_ACLK_160		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define CLK_DIV_ACLK_100		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define CLK_DIV_ACLK_266		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define CLK_DIV_CAM1			75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define CLK_DIV_CAM_BLK			76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define CLK_DIV_MFC			77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define CLK_DIV_G3D			78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define CLK_DIV_MIPI0_PRE		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define CLK_DIV_MIPI0			80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_DIV_FIMD0			81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_DIV_UART_ISP		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK_DIV_SPI1_ISP_PRE		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_DIV_SPI1_ISP		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_DIV_SPI0_ISP_PRE		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_DIV_SPI0_ISP		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_DIV_TSADC_PRE		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_DIV_TSADC			88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_DIV_MMC1_PRE		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_DIV_MMC1			90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_DIV_MMC0_PRE		91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_DIV_MMC0			92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLK_DIV_UART1			93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_DIV_UART0			94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLK_DIV_SPI1_PRE		95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_DIV_SPI1			96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_DIV_SPI0_PRE		97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_DIV_SPI0			98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLK_DIV_PCM			99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLK_DIV_AUDIO			100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLK_DIV_I2S			101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_DIV_CORE2			102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLK_DIV_APLL			103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLK_DIV_PCLK_DBG		104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLK_DIV_ATB			105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLK_DIV_COREM			106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CLK_DIV_CORE			107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLK_DIV_HPM			108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLK_DIV_COPY			109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLK_DIV_UART2			110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLK_DIV_MMC2_PRE		111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLK_DIV_MMC2			112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CLK_ASYNC_G3D			128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CLK_ASYNC_MFCL			129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CLK_PPMULEFT			130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CLK_GPIO_LEFT			131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLK_ASYNC_ISPMX			132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLK_ASYNC_FSYSD			133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLK_ASYNC_LCD0X			134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLK_ASYNC_CAMX			135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CLK_PPMURIGHT			136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CLK_GPIO_RIGHT			137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CLK_MONOCNT			138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLK_TZPC6			139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLK_PROVISIONKEY1		140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CLK_PROVISIONKEY0		141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLK_CMU_ISPPART			142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLK_TMU_APBIF			143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CLK_KEYIF			144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CLK_RTC				145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CLK_WDT				146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CLK_MCT				147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CLK_SECKEY			148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CLK_TZPC5			149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLK_TZPC4			150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CLK_TZPC3			151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CLK_TZPC2			152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CLK_TZPC1			153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CLK_TZPC0			154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CLK_CMU_COREPART		155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CLK_CMU_TOPPART			156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CLK_PMU_APBIF			157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CLK_SYSREG			158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CLK_CHIP_ID			159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLK_QEJPEG			160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CLK_PIXELASYNCM1		161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CLK_PIXELASYNCM0		162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CLK_PPMUCAMIF			163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CLK_QEM2MSCALER			164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CLK_QEGSCALER1			165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CLK_QEGSCALER0			166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CLK_SMMUJPEG			167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CLK_SMMUM2M2SCALER		168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CLK_SMMUGSCALER1		169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CLK_SMMUGSCALER0		170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CLK_JPEG			171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CLK_M2MSCALER			172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CLK_GSCALER1			173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CLK_GSCALER0			174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CLK_QEMFC			175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CLK_PPMUMFC_L			176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CLK_SMMUMFC_L			177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CLK_MFC				178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CLK_SMMUG3D			179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CLK_QEG3D			180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CLK_PPMUG3D			181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CLK_G3D				182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CLK_QE_CH1_LCD			183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CLK_QE_CH0_LCD			184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CLK_PPMULCD0			185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CLK_SMMUFIMD0			186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CLK_DSIM0			187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CLK_FIMD0			188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CLK_CAM1			189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CLK_UART_ISP_TOP		190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CLK_SPI1_ISP_TOP		191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CLK_SPI0_ISP_TOP		192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CLK_TSADC			193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CLK_PPMUFILE			194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CLK_USBOTG			195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CLK_USBHOST			196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CLK_SROMC			197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CLK_SDMMC1			198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CLK_SDMMC0			199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CLK_PDMA1			200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CLK_PDMA0			201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CLK_PWM				202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CLK_PCM				203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CLK_I2S				204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CLK_SPI1			205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CLK_SPI0			206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CLK_I2C7			207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CLK_I2C6			208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CLK_I2C5			209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CLK_I2C4			210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CLK_I2C3			211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CLK_I2C2			212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CLK_I2C1			213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CLK_I2C0			214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CLK_UART1			215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CLK_UART0			216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CLK_BLOCK_LCD			217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CLK_BLOCK_G3D			218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CLK_BLOCK_MFC			219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CLK_BLOCK_CAM			220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CLK_SMIES			221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CLK_UART2			222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CLK_SDMMC2			223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Special clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CLK_SCLK_JPEG			224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CLK_SCLK_M2MSCALER		225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CLK_SCLK_GSCALER1		226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CLK_SCLK_GSCALER0		227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CLK_SCLK_MFC			228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CLK_SCLK_G3D			229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CLK_SCLK_MIPIDPHY2L		230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CLK_SCLK_MIPI0			231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CLK_SCLK_FIMD0			232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CLK_SCLK_CAM1			233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CLK_SCLK_UART_ISP		234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CLK_SCLK_SPI1_ISP		235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CLK_SCLK_SPI0_ISP		236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CLK_SCLK_UPLL			237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define CLK_SCLK_TSADC			238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CLK_SCLK_EBI			239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define CLK_SCLK_MMC1			240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CLK_SCLK_MMC0			241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define CLK_SCLK_I2S			242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CLK_SCLK_PCM			243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CLK_SCLK_SPI1			244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define CLK_SCLK_SPI0			245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define CLK_SCLK_UART1			246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CLK_SCLK_UART0			247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CLK_SCLK_UART2			248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CLK_SCLK_MMC2			249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)  * Total number of clocks of main CMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  * NOTE: Must be equal to last clock ID increased by one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CLK_NR_CLKS			250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)  * CMU DMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CLK_FOUT_BPLL			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CLK_FOUT_EPLL			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Muxes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CLK_MOUT_MPLL_MIF		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define CLK_MOUT_BPLL			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CLK_MOUT_DPHY			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CLK_MOUT_DMC_BUS		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CLK_MOUT_EPLL			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define CLK_DIV_DMC			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CLK_DIV_DPHY			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define CLK_DIV_DMC_PRE			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CLK_DIV_DMCP			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CLK_DIV_DMCD			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)  * Total number of clocks of main CMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)  * NOTE: Must be equal to last clock ID increased by one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define NR_CLKS_DMC			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)  * CMU ISP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CLK_DIV_ISP1			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define CLK_DIV_ISP0			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define CLK_DIV_MCUISP1			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define CLK_DIV_MCUISP0			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define CLK_DIV_MPWM			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define CLK_UART_ISP			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define CLK_WDT_ISP			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define CLK_PWM_ISP			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define CLK_I2C1_ISP			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define CLK_I2C0_ISP			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define CLK_MPWM_ISP			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define CLK_MCUCTL_ISP			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define CLK_PPMUISPX			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define CLK_PPMUISPMX			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define CLK_QE_LITE1			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define CLK_QE_LITE0			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define CLK_QE_FD			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define CLK_QE_DRC			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define CLK_QE_ISP			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define CLK_CSIS1			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define CLK_SMMU_LITE1			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define CLK_SMMU_LITE0			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define CLK_SMMU_FD			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define CLK_SMMU_DRC			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define CLK_SMMU_ISP			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define CLK_GICISP			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define CLK_CSIS0			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define CLK_MCUISP			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define CLK_LITE1			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define CLK_LITE0			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define CLK_FD				33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define CLK_DRC				34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define CLK_ISP				35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define CLK_QE_ISPCX			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define CLK_QE_SCALERP			37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define CLK_QE_SCALERC			38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define CLK_SMMU_SCALERP		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define CLK_SMMU_SCALERC		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define CLK_SCALERP			41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define CLK_SCALERC			42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define CLK_SPI1_ISP			43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define CLK_SPI0_ISP			44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define CLK_SMMU_ISPCX			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define CLK_ASYNCAXIM			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define CLK_SCLK_MPWM_ISP		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)  * Total number of clocks of CMU_ISP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)  * NOTE: Must be equal to last clock ID increased by one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define NR_CLKS_ISP			48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */