^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This header provides constants for Samsung audio subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * clock controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * The constants defined in this header are being used in dts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * and exynos audss driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define EXYNOS_MOUT_AUDSS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define EXYNOS_MOUT_I2S 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define EXYNOS_DOUT_SRP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define EXYNOS_DOUT_AUD_BUS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define EXYNOS_DOUT_I2S 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define EXYNOS_SRP_CLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define EXYNOS_I2S_BUS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define EXYNOS_SCLK_I2S 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define EXYNOS_PCM_BUS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define EXYNOS_SCLK_PCM 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EXYNOS_ADMA 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EXYNOS_AUDSS_MAX_CLKS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #endif