Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2017 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #ifndef __DT_BINDINGS_CLK_DRA7_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define __DT_BINDINGS_CLK_DRA7_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define DRA7_CLKCTRL_OFFSET	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define DRA7_CLKCTRL_INDEX(offset)	((offset) - DRA7_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /* mpu clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define DRA7_MPU_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /* ipu clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define _DRA7_IPU_CLKCTRL_OFFSET	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define _DRA7_IPU_CLKCTRL_INDEX(offset)	((offset) - _DRA7_IPU_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define DRA7_MCASP1_CLKCTRL	_DRA7_IPU_CLKCTRL_INDEX(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define DRA7_TIMER5_CLKCTRL	_DRA7_IPU_CLKCTRL_INDEX(0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define DRA7_TIMER6_CLKCTRL	_DRA7_IPU_CLKCTRL_INDEX(0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define DRA7_TIMER7_CLKCTRL	_DRA7_IPU_CLKCTRL_INDEX(0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define DRA7_TIMER8_CLKCTRL	_DRA7_IPU_CLKCTRL_INDEX(0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define DRA7_I2C5_CLKCTRL	_DRA7_IPU_CLKCTRL_INDEX(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define DRA7_UART6_CLKCTRL	_DRA7_IPU_CLKCTRL_INDEX(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* rtc clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DRA7_RTC_CLKCTRL_OFFSET	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DRA7_RTC_CLKCTRL_INDEX(offset)	((offset) - DRA7_RTC_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define DRA7_RTCSS_CLKCTRL	DRA7_RTC_CLKCTRL_INDEX(0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* vip clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define DRA7_VIP1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define DRA7_VIP2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DRA7_VIP3_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /* vpe clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DRA7_VPE_CLKCTRL_OFFSET	0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define DRA7_VPE_CLKCTRL_INDEX(offset)	((offset) - DRA7_VPE_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DRA7_VPE_CLKCTRL	DRA7_VPE_CLKCTRL_INDEX(0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* coreaon clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define DRA7_SMARTREFLEX_MPU_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define DRA7_SMARTREFLEX_CORE_CLKCTRL	DRA7_CLKCTRL_INDEX(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* l3main1 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define DRA7_L3_MAIN_1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define DRA7_GPMC_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define DRA7_TPCC_CLKCTRL	DRA7_CLKCTRL_INDEX(0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define DRA7_TPTC0_CLKCTRL	DRA7_CLKCTRL_INDEX(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define DRA7_TPTC1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define DRA7_VCP1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define DRA7_VCP2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /* dma clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define DRA7_DMA_SYSTEM_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /* emif clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define DRA7_DMM_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /* atl clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define DRA7_ATL_CLKCTRL_OFFSET	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define DRA7_ATL_CLKCTRL_INDEX(offset)	((offset) - DRA7_ATL_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define DRA7_ATL_CLKCTRL	DRA7_ATL_CLKCTRL_INDEX(0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* l4cfg clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define DRA7_L4_CFG_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define DRA7_SPINLOCK_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define DRA7_MAILBOX1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define DRA7_MAILBOX2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define DRA7_MAILBOX3_CLKCTRL	DRA7_CLKCTRL_INDEX(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define DRA7_MAILBOX4_CLKCTRL	DRA7_CLKCTRL_INDEX(0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define DRA7_MAILBOX5_CLKCTRL	DRA7_CLKCTRL_INDEX(0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define DRA7_MAILBOX6_CLKCTRL	DRA7_CLKCTRL_INDEX(0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define DRA7_MAILBOX7_CLKCTRL	DRA7_CLKCTRL_INDEX(0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define DRA7_MAILBOX8_CLKCTRL	DRA7_CLKCTRL_INDEX(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define DRA7_MAILBOX9_CLKCTRL	DRA7_CLKCTRL_INDEX(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define DRA7_MAILBOX10_CLKCTRL	DRA7_CLKCTRL_INDEX(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define DRA7_MAILBOX11_CLKCTRL	DRA7_CLKCTRL_INDEX(0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define DRA7_MAILBOX12_CLKCTRL	DRA7_CLKCTRL_INDEX(0x98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define DRA7_MAILBOX13_CLKCTRL	DRA7_CLKCTRL_INDEX(0xa0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) /* l3instr clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define DRA7_L3_MAIN_2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define DRA7_L3_INSTR_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /* dss clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define DRA7_DSS_CORE_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define DRA7_BB2D_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) /* gpu clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define DRA7_GPU_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) /* l3init clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define DRA7_MMC1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define DRA7_MMC2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define DRA7_USB_OTG_SS2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define DRA7_USB_OTG_SS3_CLKCTRL	DRA7_CLKCTRL_INDEX(0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define DRA7_USB_OTG_SS4_CLKCTRL	DRA7_CLKCTRL_INDEX(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DRA7_SATA_CLKCTRL	DRA7_CLKCTRL_INDEX(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DRA7_PCIE1_CLKCTRL	DRA7_CLKCTRL_INDEX(0xb0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DRA7_PCIE2_CLKCTRL	DRA7_CLKCTRL_INDEX(0xb8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DRA7_GMAC_CLKCTRL	DRA7_CLKCTRL_INDEX(0xd0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DRA7_OCP2SCP1_CLKCTRL	DRA7_CLKCTRL_INDEX(0xe0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DRA7_OCP2SCP3_CLKCTRL	DRA7_CLKCTRL_INDEX(0xe8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DRA7_USB_OTG_SS1_CLKCTRL	DRA7_CLKCTRL_INDEX(0xf0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* l4per clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define _DRA7_L4PER_CLKCTRL_OFFSET	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define _DRA7_L4PER_CLKCTRL_INDEX(offset)	((offset) - _DRA7_L4PER_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DRA7_L4_PER2_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DRA7_L4_PER3_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DRA7_TIMER10_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DRA7_TIMER11_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DRA7_TIMER2_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DRA7_TIMER3_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DRA7_TIMER4_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DRA7_TIMER9_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DRA7_ELM_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DRA7_GPIO2_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DRA7_GPIO3_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DRA7_GPIO4_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DRA7_GPIO5_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DRA7_GPIO6_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DRA7_HDQ1W_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DRA7_EPWMSS1_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DRA7_EPWMSS2_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DRA7_I2C1_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0xa0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DRA7_I2C2_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0xa8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DRA7_I2C3_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0xb0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DRA7_I2C4_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0xb8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DRA7_L4_PER1_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DRA7_EPWMSS0_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0xc4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DRA7_TIMER13_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0xc8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DRA7_TIMER14_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0xd0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DRA7_TIMER15_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0xd8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DRA7_MCSPI1_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0xf0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DRA7_MCSPI2_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0xf8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DRA7_MCSPI3_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DRA7_MCSPI4_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DRA7_GPIO7_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DRA7_GPIO8_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DRA7_MMC3_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DRA7_MMC4_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DRA7_TIMER16_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DRA7_QSPI_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DRA7_UART1_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define DRA7_UART2_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DRA7_UART3_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DRA7_UART4_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DRA7_MCASP2_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DRA7_MCASP3_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DRA7_UART5_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DRA7_MCASP5_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DRA7_MCASP8_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DRA7_MCASP4_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DRA7_AES1_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x1a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DRA7_AES2_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x1a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DRA7_DES_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x1b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DRA7_RNG_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x1c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DRA7_SHAM_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x1c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DRA7_UART7_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x1d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DRA7_UART8_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x1e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DRA7_UART9_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x1e8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DRA7_DCAN2_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x1f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DRA7_MCASP6_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DRA7_MCASP7_CLKCTRL	_DRA7_L4PER_CLKCTRL_INDEX(0x208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* wkupaon clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DRA7_L4_WKUP_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DRA7_WD_TIMER2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DRA7_GPIO1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DRA7_TIMER1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DRA7_TIMER12_CLKCTRL	DRA7_CLKCTRL_INDEX(0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DRA7_COUNTER_32K_CLKCTRL	DRA7_CLKCTRL_INDEX(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DRA7_UART10_CLKCTRL	DRA7_CLKCTRL_INDEX(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DRA7_DCAN1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DRA7_ADC_CLKCTRL	DRA7_CLKCTRL_INDEX(0xa0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* XXX: Compatibility part end. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* mpu clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define DRA7_MPU_MPU_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* dsp1 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define DRA7_DSP1_MMU0_DSP1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* ipu1 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define DRA7_IPU1_MMU_IPU1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* ipu clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define DRA7_IPU_CLKCTRL_OFFSET	0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define DRA7_IPU_CLKCTRL_INDEX(offset)	((offset) - DRA7_IPU_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DRA7_IPU_MCASP1_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DRA7_IPU_TIMER5_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DRA7_IPU_TIMER6_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define DRA7_IPU_TIMER7_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define DRA7_IPU_TIMER8_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define DRA7_IPU_I2C5_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define DRA7_IPU_UART6_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* dsp2 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define DRA7_DSP2_MMU0_DSP2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* rtc clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define DRA7_RTC_RTCSS_CLKCTRL	DRA7_CLKCTRL_INDEX(0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* vip clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define DRA7_CAM_VIP1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define DRA7_CAM_VIP2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define DRA7_CAM_VIP3_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* vpe clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define DRA7_VPE_CLKCTRL_OFFSET	0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define DRA7_VPE_CLKCTRL_INDEX(offset)	((offset) - DRA7_VPE_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define DRA7_VPE_VPE_CLKCTRL	DRA7_VPE_CLKCTRL_INDEX(0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* coreaon clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL	DRA7_CLKCTRL_INDEX(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* l3main1 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define DRA7_L3MAIN1_GPMC_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define DRA7_L3MAIN1_TPCC_CLKCTRL	DRA7_CLKCTRL_INDEX(0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define DRA7_L3MAIN1_TPTC0_CLKCTRL	DRA7_CLKCTRL_INDEX(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define DRA7_L3MAIN1_TPTC1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define DRA7_L3MAIN1_VCP1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define DRA7_L3MAIN1_VCP2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* ipu2 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define DRA7_IPU2_MMU_IPU2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* dma clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define DRA7_DMA_DMA_SYSTEM_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* emif clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define DRA7_EMIF_DMM_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* atl clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define DRA7_ATL_CLKCTRL_OFFSET	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define DRA7_ATL_CLKCTRL_INDEX(offset)	((offset) - DRA7_ATL_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define DRA7_ATL_ATL_CLKCTRL	DRA7_ATL_CLKCTRL_INDEX(0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* l4cfg clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define DRA7_L4CFG_L4_CFG_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define DRA7_L4CFG_SPINLOCK_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define DRA7_L4CFG_MAILBOX1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define DRA7_L4CFG_MAILBOX2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define DRA7_L4CFG_MAILBOX3_CLKCTRL	DRA7_CLKCTRL_INDEX(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define DRA7_L4CFG_MAILBOX4_CLKCTRL	DRA7_CLKCTRL_INDEX(0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define DRA7_L4CFG_MAILBOX5_CLKCTRL	DRA7_CLKCTRL_INDEX(0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define DRA7_L4CFG_MAILBOX6_CLKCTRL	DRA7_CLKCTRL_INDEX(0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define DRA7_L4CFG_MAILBOX7_CLKCTRL	DRA7_CLKCTRL_INDEX(0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define DRA7_L4CFG_MAILBOX8_CLKCTRL	DRA7_CLKCTRL_INDEX(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define DRA7_L4CFG_MAILBOX9_CLKCTRL	DRA7_CLKCTRL_INDEX(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define DRA7_L4CFG_MAILBOX10_CLKCTRL	DRA7_CLKCTRL_INDEX(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define DRA7_L4CFG_MAILBOX11_CLKCTRL	DRA7_CLKCTRL_INDEX(0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define DRA7_L4CFG_MAILBOX12_CLKCTRL	DRA7_CLKCTRL_INDEX(0x98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define DRA7_L4CFG_MAILBOX13_CLKCTRL	DRA7_CLKCTRL_INDEX(0xa0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* l3instr clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define DRA7_L3INSTR_L3_INSTR_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* dss clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define DRA7_DSS_DSS_CORE_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define DRA7_DSS_BB2D_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* l3init clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define DRA7_L3INIT_MMC1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define DRA7_L3INIT_MMC2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define DRA7_L3INIT_USB_OTG_SS2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define DRA7_L3INIT_USB_OTG_SS3_CLKCTRL	DRA7_CLKCTRL_INDEX(0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define DRA7_L3INIT_USB_OTG_SS4_CLKCTRL	DRA7_CLKCTRL_INDEX(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define DRA7_L3INIT_SATA_CLKCTRL	DRA7_CLKCTRL_INDEX(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define DRA7_L3INIT_OCP2SCP1_CLKCTRL	DRA7_CLKCTRL_INDEX(0xe0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define DRA7_L3INIT_OCP2SCP3_CLKCTRL	DRA7_CLKCTRL_INDEX(0xe8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define DRA7_L3INIT_USB_OTG_SS1_CLKCTRL	DRA7_CLKCTRL_INDEX(0xf0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* pcie clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define DRA7_PCIE_CLKCTRL_OFFSET	0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define DRA7_PCIE_CLKCTRL_INDEX(offset)	((offset) - DRA7_PCIE_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define DRA7_PCIE_PCIE1_CLKCTRL	DRA7_PCIE_CLKCTRL_INDEX(0xb0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define DRA7_PCIE_PCIE2_CLKCTRL	DRA7_PCIE_CLKCTRL_INDEX(0xb8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* gmac clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define DRA7_GMAC_CLKCTRL_OFFSET	0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define DRA7_GMAC_CLKCTRL_INDEX(offset)	((offset) - DRA7_GMAC_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define DRA7_GMAC_GMAC_CLKCTRL	DRA7_GMAC_CLKCTRL_INDEX(0xd0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* l4per clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define DRA7_L4PER_CLKCTRL_OFFSET	0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define DRA7_L4PER_CLKCTRL_INDEX(offset)	((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define DRA7_L4PER_TIMER10_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define DRA7_L4PER_TIMER11_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define DRA7_L4PER_TIMER2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define DRA7_L4PER_TIMER3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define DRA7_L4PER_TIMER4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define DRA7_L4PER_TIMER9_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define DRA7_L4PER_ELM_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DRA7_L4PER_GPIO2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define DRA7_L4PER_GPIO3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define DRA7_L4PER_GPIO4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define DRA7_L4PER_GPIO5_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define DRA7_L4PER_GPIO6_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define DRA7_L4PER_HDQ1W_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define DRA7_L4PER_I2C1_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xa0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define DRA7_L4PER_I2C2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xa8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define DRA7_L4PER_I2C3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xb0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define DRA7_L4PER_I2C4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xb8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define DRA7_L4PER_L4_PER1_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define DRA7_L4PER_MCSPI1_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xf0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define DRA7_L4PER_MCSPI2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xf8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define DRA7_L4PER_MCSPI3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define DRA7_L4PER_MCSPI4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define DRA7_L4PER_GPIO7_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define DRA7_L4PER_GPIO8_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define DRA7_L4PER_MMC3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define DRA7_L4PER_MMC4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define DRA7_L4PER_UART1_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define DRA7_L4PER_UART2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define DRA7_L4PER_UART3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define DRA7_L4PER_UART4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define DRA7_L4PER_UART5_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* l4sec clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define DRA7_L4SEC_CLKCTRL_OFFSET	0x1a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define DRA7_L4SEC_CLKCTRL_INDEX(offset)	((offset) - DRA7_L4SEC_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define DRA7_L4SEC_AES1_CLKCTRL	DRA7_L4SEC_CLKCTRL_INDEX(0x1a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define DRA7_L4SEC_AES2_CLKCTRL	DRA7_L4SEC_CLKCTRL_INDEX(0x1a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define DRA7_L4SEC_DES_CLKCTRL	DRA7_L4SEC_CLKCTRL_INDEX(0x1b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define DRA7_L4SEC_RNG_CLKCTRL	DRA7_L4SEC_CLKCTRL_INDEX(0x1c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define DRA7_L4SEC_SHAM_CLKCTRL	DRA7_L4SEC_CLKCTRL_INDEX(0x1c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define DRA7_L4SEC_SHAM2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1f8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* l4per2 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define DRA7_L4PER2_CLKCTRL_OFFSET	0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define DRA7_L4PER2_CLKCTRL_INDEX(offset)	((offset) - DRA7_L4PER2_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define DRA7_L4PER2_L4_PER2_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define DRA7_L4PER2_PRUSS1_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define DRA7_L4PER2_PRUSS2_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define DRA7_L4PER2_EPWMSS1_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define DRA7_L4PER2_EPWMSS2_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define DRA7_L4PER2_EPWMSS0_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0xc4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define DRA7_L4PER2_QSPI_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define DRA7_L4PER2_MCASP2_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define DRA7_L4PER2_MCASP3_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define DRA7_L4PER2_MCASP5_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define DRA7_L4PER2_MCASP8_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define DRA7_L4PER2_MCASP4_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define DRA7_L4PER2_UART7_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x1d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define DRA7_L4PER2_UART8_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x1e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define DRA7_L4PER2_UART9_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x1e8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define DRA7_L4PER2_DCAN2_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x1f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define DRA7_L4PER2_MCASP6_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define DRA7_L4PER2_MCASP7_CLKCTRL	DRA7_L4PER2_CLKCTRL_INDEX(0x208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* l4per3 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define DRA7_L4PER3_CLKCTRL_OFFSET	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define DRA7_L4PER3_CLKCTRL_INDEX(offset)	((offset) - DRA7_L4PER3_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define DRA7_L4PER3_L4_PER3_CLKCTRL	DRA7_L4PER3_CLKCTRL_INDEX(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define DRA7_L4PER3_TIMER13_CLKCTRL	DRA7_L4PER3_CLKCTRL_INDEX(0xc8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define DRA7_L4PER3_TIMER14_CLKCTRL	DRA7_L4PER3_CLKCTRL_INDEX(0xd0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define DRA7_L4PER3_TIMER15_CLKCTRL	DRA7_L4PER3_CLKCTRL_INDEX(0xd8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define DRA7_L4PER3_TIMER16_CLKCTRL	DRA7_L4PER3_CLKCTRL_INDEX(0x130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* wkupaon clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define DRA7_WKUPAON_L4_WKUP_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define DRA7_WKUPAON_WD_TIMER2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define DRA7_WKUPAON_GPIO1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define DRA7_WKUPAON_TIMER1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define DRA7_WKUPAON_TIMER12_CLKCTRL	DRA7_CLKCTRL_INDEX(0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define DRA7_WKUPAON_COUNTER_32K_CLKCTRL	DRA7_CLKCTRL_INDEX(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define DRA7_WKUPAON_UART10_CLKCTRL	DRA7_CLKCTRL_INDEX(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define DRA7_WKUPAON_DCAN1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define DRA7_WKUPAON_ADC_CLKCTRL	DRA7_CLKCTRL_INDEX(0xa0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #endif