Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2017 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #ifndef __DT_BINDINGS_CLK_DM816_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define __DT_BINDINGS_CLK_DM816_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define DM816_CLKCTRL_OFFSET	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define DM816_CLKCTRL_INDEX(offset)	((offset) - DM816_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* default clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DM816_USB_OTG_HS_CLKCTRL	DM816_CLKCTRL_INDEX(0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* alwon clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DM816_UART1_CLKCTRL	DM816_CLKCTRL_INDEX(0x150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DM816_UART2_CLKCTRL	DM816_CLKCTRL_INDEX(0x154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DM816_UART3_CLKCTRL	DM816_CLKCTRL_INDEX(0x158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DM816_GPIO1_CLKCTRL	DM816_CLKCTRL_INDEX(0x15c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DM816_GPIO2_CLKCTRL	DM816_CLKCTRL_INDEX(0x160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DM816_I2C1_CLKCTRL	DM816_CLKCTRL_INDEX(0x164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DM816_I2C2_CLKCTRL	DM816_CLKCTRL_INDEX(0x168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DM816_TIMER1_CLKCTRL	DM816_CLKCTRL_INDEX(0x170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DM816_TIMER2_CLKCTRL	DM816_CLKCTRL_INDEX(0x174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DM816_TIMER3_CLKCTRL	DM816_CLKCTRL_INDEX(0x178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DM816_TIMER4_CLKCTRL	DM816_CLKCTRL_INDEX(0x17c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DM816_TIMER5_CLKCTRL	DM816_CLKCTRL_INDEX(0x180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DM816_TIMER6_CLKCTRL	DM816_CLKCTRL_INDEX(0x184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DM816_TIMER7_CLKCTRL	DM816_CLKCTRL_INDEX(0x188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DM816_WD_TIMER_CLKCTRL	DM816_CLKCTRL_INDEX(0x18c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DM816_MCSPI1_CLKCTRL	DM816_CLKCTRL_INDEX(0x190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DM816_MAILBOX_CLKCTRL	DM816_CLKCTRL_INDEX(0x194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DM816_SPINBOX_CLKCTRL	DM816_CLKCTRL_INDEX(0x198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DM816_MMC1_CLKCTRL	DM816_CLKCTRL_INDEX(0x1b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DM816_GPMC_CLKCTRL	DM816_CLKCTRL_INDEX(0x1d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DM816_DAVINCI_MDIO_CLKCTRL	DM816_CLKCTRL_INDEX(0x1d4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DM816_EMAC1_CLKCTRL	DM816_CLKCTRL_INDEX(0x1d8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DM816_MPU_CLKCTRL	DM816_CLKCTRL_INDEX(0x1dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DM816_RTC_CLKCTRL	DM816_CLKCTRL_INDEX(0x1f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DM816_TPCC_CLKCTRL	DM816_CLKCTRL_INDEX(0x1f4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DM816_TPTC0_CLKCTRL	DM816_CLKCTRL_INDEX(0x1f8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DM816_TPTC1_CLKCTRL	DM816_CLKCTRL_INDEX(0x1fc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DM816_TPTC2_CLKCTRL	DM816_CLKCTRL_INDEX(0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DM816_TPTC3_CLKCTRL	DM816_CLKCTRL_INDEX(0x204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #endif