Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2017 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #ifndef __DT_BINDINGS_CLK_DM814_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define __DT_BINDINGS_CLK_DM814_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define DM814_CLKCTRL_OFFSET	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define DM814_CLKCTRL_INDEX(offset)	((offset) - DM814_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* default clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DM814_USB_OTG_HS_CLKCTRL	DM814_CLKCTRL_INDEX(0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* alwon clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DM814_UART1_CLKCTRL	DM814_CLKCTRL_INDEX(0x150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DM814_UART2_CLKCTRL	DM814_CLKCTRL_INDEX(0x154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DM814_UART3_CLKCTRL	DM814_CLKCTRL_INDEX(0x158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DM814_GPIO1_CLKCTRL	DM814_CLKCTRL_INDEX(0x15c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DM814_GPIO2_CLKCTRL	DM814_CLKCTRL_INDEX(0x160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DM814_I2C1_CLKCTRL	DM814_CLKCTRL_INDEX(0x164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DM814_I2C2_CLKCTRL	DM814_CLKCTRL_INDEX(0x168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DM814_WD_TIMER_CLKCTRL	DM814_CLKCTRL_INDEX(0x18c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DM814_MCSPI1_CLKCTRL	DM814_CLKCTRL_INDEX(0x190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DM814_GPMC_CLKCTRL	DM814_CLKCTRL_INDEX(0x1d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DM814_CPGMAC0_CLKCTRL	DM814_CLKCTRL_INDEX(0x1d4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DM814_MPU_CLKCTRL	DM814_CLKCTRL_INDEX(0x1dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DM814_RTC_CLKCTRL	DM814_CLKCTRL_INDEX(0x1f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DM814_TPCC_CLKCTRL	DM814_CLKCTRL_INDEX(0x1f4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DM814_TPTC0_CLKCTRL	DM814_CLKCTRL_INDEX(0x1f8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DM814_TPTC1_CLKCTRL	DM814_CLKCTRL_INDEX(0x1fc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DM814_TPTC2_CLKCTRL	DM814_CLKCTRL_INDEX(0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DM814_TPTC3_CLKCTRL	DM814_CLKCTRL_INDEX(0x204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DM814_MMC1_CLKCTRL	DM814_CLKCTRL_INDEX(0x21c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DM814_MMC2_CLKCTRL	DM814_CLKCTRL_INDEX(0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DM814_MMC3_CLKCTRL	DM814_CLKCTRL_INDEX(0x224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* alwon_ethernet clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DM814_ETHERNET_CLKCTRL_OFFSET	0x1d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DM814_ETHERNET_CLKCTRL_INDEX(offset)	((offset) - DM814_ETHERNET_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DM814_ETHERNET_CPGMAC0_CLKCTRL	DM814_ETHERNET_CLKCTRL_INDEX(0x1d4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif