^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __DT_BINDINGS_CLOCK_CLPS711X_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __DT_BINDINGS_CLOCK_CLPS711X_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define CLPS711X_CLK_DUMMY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CLPS711X_CLK_CPU 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CLPS711X_CLK_BUS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CLPS711X_CLK_PLL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLPS711X_CLK_TIMERREF 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLPS711X_CLK_TIMER1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLPS711X_CLK_TIMER2 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLPS711X_CLK_PWM 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLPS711X_CLK_SPIREF 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLPS711X_CLK_SPI 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLPS711X_CLK_UART 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLPS711X_CLK_TICK 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLPS711X_CLK_MAX 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #endif