Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Baikal-T1 CCU clock indices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef __DT_BINDINGS_CLOCK_BT1_CCU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define __DT_BINDINGS_CLOCK_BT1_CCU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CCU_CPU_PLL			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CCU_SATA_PLL			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CCU_DDR_PLL			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CCU_PCIE_PLL			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CCU_ETH_PLL			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CCU_AXI_MAIN_CLK		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CCU_AXI_DDR_CLK			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CCU_AXI_SATA_CLK		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CCU_AXI_GMAC0_CLK		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CCU_AXI_GMAC1_CLK		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CCU_AXI_XGMAC_CLK		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CCU_AXI_PCIE_M_CLK		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CCU_AXI_PCIE_S_CLK		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CCU_AXI_USB_CLK			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CCU_AXI_HWA_CLK			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CCU_AXI_SRAM_CLK		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CCU_SYS_SATA_REF_CLK		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CCU_SYS_APB_CLK			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CCU_SYS_GMAC0_TX_CLK		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CCU_SYS_GMAC0_PTP_CLK		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CCU_SYS_GMAC1_TX_CLK		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CCU_SYS_GMAC1_PTP_CLK		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CCU_SYS_XGMAC_REF_CLK		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CCU_SYS_XGMAC_PTP_CLK		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CCU_SYS_USB_CLK			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CCU_SYS_PVT_CLK			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CCU_SYS_HWA_CLK			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CCU_SYS_UART_CLK		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CCU_SYS_I2C1_CLK		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CCU_SYS_I2C2_CLK		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CCU_SYS_GPIO_CLK		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CCU_SYS_TIMER0_CLK		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CCU_SYS_TIMER1_CLK		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CCU_SYS_TIMER2_CLK		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CCU_SYS_WDT_CLK			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif /* __DT_BINDINGS_CLOCK_BT1_CCU_H */