Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Device Tree binding constants for Bitmain BM1880 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2019 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef __DT_BINDINGS_CLOCK_BM1880_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define __DT_BINDINGS_CLOCK_BM1880_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define BM1880_CLK_OSC			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define BM1880_CLK_MPLL			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define BM1880_CLK_SPLL			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define BM1880_CLK_FPLL			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define BM1880_CLK_DDRPLL		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define BM1880_CLK_A53			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BM1880_CLK_50M_A53		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BM1880_CLK_AHB_ROM		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BM1880_CLK_AXI_SRAM		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BM1880_CLK_DDR_AXI		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BM1880_CLK_EFUSE		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BM1880_CLK_APB_EFUSE		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BM1880_CLK_AXI5_EMMC		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BM1880_CLK_EMMC			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BM1880_CLK_100K_EMMC		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BM1880_CLK_AXI5_SD		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BM1880_CLK_SD			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BM1880_CLK_100K_SD		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BM1880_CLK_500M_ETH0		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BM1880_CLK_AXI4_ETH0		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BM1880_CLK_500M_ETH1		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BM1880_CLK_AXI4_ETH1		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BM1880_CLK_AXI1_GDMA		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BM1880_CLK_APB_GPIO		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BM1880_CLK_APB_GPIO_INTR	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BM1880_CLK_GPIO_DB		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BM1880_CLK_AXI1_MINER		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BM1880_CLK_AHB_SF		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BM1880_CLK_SDMA_AXI		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BM1880_CLK_SDMA_AUD		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BM1880_CLK_APB_I2C		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BM1880_CLK_APB_WDT		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BM1880_CLK_APB_JPEG		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BM1880_CLK_JPEG_AXI		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BM1880_CLK_AXI5_NF		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BM1880_CLK_APB_NF		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BM1880_CLK_NF			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BM1880_CLK_APB_PWM		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BM1880_CLK_DIV_0_RV		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BM1880_CLK_DIV_1_RV		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BM1880_CLK_MUX_RV		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BM1880_CLK_RV			41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BM1880_CLK_APB_SPI		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BM1880_CLK_TPU_AXI		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BM1880_CLK_DIV_UART_500M	44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define BM1880_CLK_UART_500M		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BM1880_CLK_APB_UART		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BM1880_CLK_APB_I2S		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BM1880_CLK_AXI4_USB		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BM1880_CLK_APB_USB		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BM1880_CLK_125M_USB		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define BM1880_CLK_33K_USB		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define BM1880_CLK_DIV_12M_USB		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define BM1880_CLK_12M_USB		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define BM1880_CLK_APB_VIDEO		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define BM1880_CLK_VIDEO_AXI		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define BM1880_CLK_VPP_AXI		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define BM1880_CLK_APB_VPP		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define BM1880_CLK_DIV_0_AXI1		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BM1880_CLK_DIV_1_AXI1		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define BM1880_CLK_AXI1			60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define BM1880_CLK_AXI2			61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BM1880_CLK_AXI3			62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define BM1880_CLK_AXI4			63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define BM1880_CLK_AXI5			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define BM1880_CLK_DIV_0_AXI6		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define BM1880_CLK_DIV_1_AXI6		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define BM1880_CLK_MUX_AXI6		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define BM1880_CLK_AXI6			68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define BM1880_NR_CLKS			69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif /* __DT_BINDINGS_CLOCK_BM1880_H */