^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #ifndef __DT_BINDINGS_CLOCK_BCM6362_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #define __DT_BINDINGS_CLOCK_BCM6362_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define BCM6362_CLK_ADSL_QPROC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define BCM6362_CLK_ADSL_AFE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define BCM6362_CLK_ADSL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define BCM6362_CLK_MIPS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define BCM6362_CLK_WLAN_OCP 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define BCM6362_CLK_SWPKT_USB 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define BCM6362_CLK_SWPKT_SAR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define BCM6362_CLK_SAR 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define BCM6362_CLK_ROBOSW 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define BCM6362_CLK_PCM 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define BCM6362_CLK_USBD 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BCM6362_CLK_USBH 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BCM6362_CLK_IPSEC 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BCM6362_CLK_SPI 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BCM6362_CLK_HSSPI 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BCM6362_CLK_PCIE 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BCM6362_CLK_FAP 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BCM6362_CLK_PHYMIPS 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BCM6362_CLK_NAND 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #endif /* __DT_BINDINGS_CLOCK_BCM6362_H */