^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #ifndef __DT_BINDINGS_CLOCK_BCM6328_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #define __DT_BINDINGS_CLOCK_BCM6328_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define BCM6328_CLK_PHYMIPS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define BCM6328_CLK_ADSL_QPROC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define BCM6328_CLK_ADSL_AFE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define BCM6328_CLK_ADSL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define BCM6328_CLK_MIPS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define BCM6328_CLK_SAR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define BCM6328_CLK_PCM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define BCM6328_CLK_USBD 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define BCM6328_CLK_USBH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define BCM6328_CLK_HSSPI 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define BCM6328_CLK_PCIE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BCM6328_CLK_ROBOSW 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #endif /* __DT_BINDINGS_CLOCK_BCM6328_H */