Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #ifndef __DT_BINDINGS_CLOCK_BCM6318_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #define __DT_BINDINGS_CLOCK_BCM6318_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define BCM6318_CLK_ADSL_ASB	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define BCM6318_CLK_USB_ASB	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define BCM6318_CLK_MIPS_ASB	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define BCM6318_CLK_PCIE_ASB	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define BCM6318_CLK_PHYMIPS_ASB	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define BCM6318_CLK_ROBOSW_ASB	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define BCM6318_CLK_SAR_ASB	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define BCM6318_CLK_SDR_ASB	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define BCM6318_CLK_SWREG_ASB	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define BCM6318_CLK_PERIPH_ASB	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define BCM6318_CLK_CPUBUS160	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BCM6318_CLK_ADSL	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BCM6318_CLK_SAR125	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BCM6318_CLK_MIPS	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BCM6318_CLK_PCIE	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BCM6318_CLK_ROBOSW250	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BCM6318_CLK_ROBOSW025	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BCM6318_CLK_SDR		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BCM6318_CLK_USBD	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BCM6318_CLK_HSSPI	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BCM6318_CLK_PCIE25	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BCM6318_CLK_PHYMIPS	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BCM6318_CLK_AFE		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BCM6318_CLK_QPROC	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BCM6318_UCLK_ADSL	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BCM6318_UCLK_ARB	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BCM6318_UCLK_MIPS	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BCM6318_UCLK_PCIE	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BCM6318_UCLK_PERIPH	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BCM6318_UCLK_PHYMIPS	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BCM6318_UCLK_ROBOSW	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BCM6318_UCLK_SAR	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BCM6318_UCLK_SDR	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BCM6318_UCLK_USB	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif /* __DT_BINDINGS_CLOCK_BCM6318_H */