Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * Copyright (C) 2013 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2013 Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifndef _CLOCK_BCM281XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define _CLOCK_BCM281XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * This file defines the values used to specify clocks provided by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * the clock control units (CCUs) on Broadcom BCM281XX family SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * These are the bcm281xx CCU device tree "compatible" strings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  * We're stuck with using "bcm11351" in the string because wild
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  * cards aren't allowed, and that name was the first one defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  * in this family of devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BCM281XX_DT_ROOT_CCU_COMPAT	"brcm,bcm11351-root-ccu"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BCM281XX_DT_AON_CCU_COMPAT	"brcm,bcm11351-aon-ccu"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BCM281XX_DT_HUB_CCU_COMPAT	"brcm,bcm11351-hub-ccu"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BCM281XX_DT_MASTER_CCU_COMPAT	"brcm,bcm11351-master-ccu"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BCM281XX_DT_SLAVE_CCU_COMPAT	"brcm,bcm11351-slave-ccu"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* root CCU clock ids */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BCM281XX_ROOT_CCU_FRAC_1M		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BCM281XX_ROOT_CCU_CLOCK_COUNT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* aon CCU clock ids */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BCM281XX_AON_CCU_HUB_TIMER		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BCM281XX_AON_CCU_PMU_BSC		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BCM281XX_AON_CCU_PMU_BSC_VAR		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BCM281XX_AON_CCU_CLOCK_COUNT		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* hub CCU clock ids */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BCM281XX_HUB_CCU_TMON_1M		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BCM281XX_HUB_CCU_CLOCK_COUNT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* master CCU clock ids */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BCM281XX_MASTER_CCU_SDIO1		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BCM281XX_MASTER_CCU_SDIO2		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define BCM281XX_MASTER_CCU_SDIO3		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BCM281XX_MASTER_CCU_SDIO4		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BCM281XX_MASTER_CCU_USB_IC		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BCM281XX_MASTER_CCU_HSIC2_48M		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BCM281XX_MASTER_CCU_HSIC2_12M		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BCM281XX_MASTER_CCU_CLOCK_COUNT		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* slave CCU clock ids */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define BCM281XX_SLAVE_CCU_UARTB		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define BCM281XX_SLAVE_CCU_UARTB2		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define BCM281XX_SLAVE_CCU_UARTB3		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define BCM281XX_SLAVE_CCU_UARTB4		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define BCM281XX_SLAVE_CCU_SSP0			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BCM281XX_SLAVE_CCU_SSP2			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define BCM281XX_SLAVE_CCU_BSC1			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define BCM281XX_SLAVE_CCU_BSC2			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BCM281XX_SLAVE_CCU_BSC3			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define BCM281XX_SLAVE_CCU_PWM			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define BCM281XX_SLAVE_CCU_CLOCK_COUNT		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #endif /* _CLOCK_BCM281XX_H */