^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * BSD LICENSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright(c) 2017 Broadcom. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * * Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * * Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * notice, this list of conditions and the following disclaimer in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * the documentation and/or other materials provided with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * * Neither the name of Broadcom Corporation nor the names of its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * contributors may be used to endorse or promote products derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #ifndef _CLOCK_BCM_SR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define _CLOCK_BCM_SR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* GENPLL 0 clock channel ID SCR HSLS FS PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BCM_SR_GENPLL0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BCM_SR_GENPLL0_125M_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BCM_SR_GENPLL0_SCR_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BCM_SR_GENPLL0_250M_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BCM_SR_GENPLL0_PCIE_AXI_CLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BCM_SR_GENPLL0_PAXC_AXI_X2_CLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BCM_SR_GENPLL0_PAXC_AXI_CLK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* GENPLL 1 clock channel ID MHB PCIE NITRO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BCM_SR_GENPLL1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BCM_SR_GENPLL1_PCIE_TL_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BCM_SR_GENPLL1_MHB_APB_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* GENPLL 2 clock channel ID NITRO MHB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BCM_SR_GENPLL2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BCM_SR_GENPLL2_NIC_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BCM_SR_GENPLL2_TS_500_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BCM_SR_GENPLL2_125_NITRO_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BCM_SR_GENPLL2_CHIMP_CLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define BCM_SR_GENPLL2_NIC_FLASH_CLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BCM_SR_GENPLL2_FS4_CLK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* GENPLL 3 HSLS clock channel ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BCM_SR_GENPLL3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BCM_SR_GENPLL3_HSLS_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define BCM_SR_GENPLL3_SDIO_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* GENPLL 4 SCR clock channel ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define BCM_SR_GENPLL4 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define BCM_SR_GENPLL4_CCN_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define BCM_SR_GENPLL4_TPIU_PLL_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define BCM_SR_GENPLL4_NOC_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define BCM_SR_GENPLL4_CHCLK_FS4_CLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* GENPLL 5 FS4 clock channel ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BCM_SR_GENPLL5 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define BCM_SR_GENPLL5_FS4_HF_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define BCM_SR_GENPLL5_CRYPTO_AE_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define BCM_SR_GENPLL5_RAID_AE_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* GENPLL 6 NITRO clock channel ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define BCM_SR_GENPLL6 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define BCM_SR_GENPLL6_48_USB_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* LCPLL0 clock channel ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define BCM_SR_LCPLL0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define BCM_SR_LCPLL0_SATA_REFP_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define BCM_SR_LCPLL0_SATA_REFN_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define BCM_SR_LCPLL0_SATA_350_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define BCM_SR_LCPLL0_SATA_500_CLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* LCPLL1 clock channel ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define BCM_SR_LCPLL1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define BCM_SR_LCPLL1_WAN_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define BCM_SR_LCPLL1_USB_REF_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define BCM_SR_LCPLL1_CRMU_TS_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* LCPLL PCIE clock channel ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define BCM_SR_LCPLL_PCIE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define BCM_SR_LCPLL_PCIE_PHY_REF_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* GENPLL EMEM0 clock channel ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define BCM_SR_EMEMPLL0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define BCM_SR_EMEMPLL0_EMEM_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* GENPLL EMEM0 clock channel ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BCM_SR_EMEMPLL1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define BCM_SR_EMEMPLL1_EMEM_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* GENPLL EMEM0 clock channel ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define BCM_SR_EMEMPLL2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BCM_SR_EMEMPLL2_EMEM_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #endif /* _CLOCK_BCM_SR_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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