Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * ARTPEC-6 clock controller indexes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright 2016 Axis Comunications AB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ARTPEC6_CLK_CPU			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ARTPEC6_CLK_CPU_PERIPH		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ARTPEC6_CLK_NAND_CLKA		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define ARTPEC6_CLK_NAND_CLKB		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ARTPEC6_CLK_ETH_ACLK		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ARTPEC6_CLK_DMA_ACLK		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ARTPEC6_CLK_PTP_REF		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ARTPEC6_CLK_SD_PCLK		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ARTPEC6_CLK_SD_IMCLK		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ARTPEC6_CLK_I2S_HST		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ARTPEC6_CLK_I2S0_CLK		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ARTPEC6_CLK_I2S1_CLK		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ARTPEC6_CLK_UART_PCLK		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ARTPEC6_CLK_UART_REFCLK		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ARTPEC6_CLK_I2C			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ARTPEC6_CLK_SPI_PCLK		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ARTPEC6_CLK_SPI_SSPCLK		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ARTPEC6_CLK_SYS_TIMER		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ARTPEC6_CLK_FRACDIV_IN		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ARTPEC6_CLK_DBG_PCLK		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* This must be the highest clock index plus one. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ARTPEC6_CLK_NUMCLOCKS		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif