Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Meson-AXG clock tree IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef __AXG_CLKC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define __AXG_CLKC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CLKID_SYS_PLL				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CLKID_FIXED_PLL				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLKID_FCLK_DIV2				2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLKID_FCLK_DIV3				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLKID_FCLK_DIV4				4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLKID_FCLK_DIV5				5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLKID_FCLK_DIV7				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLKID_GP0_PLL				7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLKID_CLK81				10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLKID_MPLL0				11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLKID_MPLL1				12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLKID_MPLL2				13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLKID_MPLL3				14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLKID_DDR				15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLKID_AUDIO_LOCKER			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLKID_MIPI_DSI_HOST			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLKID_ISA				18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLKID_PL301				19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLKID_PERIPHS				20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLKID_SPICC0				21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLKID_I2C				22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLKID_RNG0				23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLKID_UART0				24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLKID_MIPI_DSI_PHY			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLKID_SPICC1				26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLKID_PCIE_A				27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLKID_PCIE_B				28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLKID_HIU_IFACE				29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLKID_ASSIST_MISC			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLKID_SD_EMMC_B				31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLKID_SD_EMMC_C				32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLKID_DMA				33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLKID_SPI				34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLKID_AUDIO				35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLKID_ETH				36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLKID_UART1				37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLKID_G2D				38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLKID_USB0				39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLKID_USB1				40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLKID_RESET				41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLKID_USB				42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLKID_AHB_ARB0				43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLKID_EFUSE				44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLKID_BOOT_ROM				45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLKID_AHB_DATA_BUS			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLKID_AHB_CTRL_BUS			47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLKID_USB1_DDR_BRIDGE			48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLKID_USB0_DDR_BRIDGE			49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLKID_MMC_PCLK				50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLKID_VPU_INTR				51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLKID_SEC_AHB_AHB3_BRIDGE		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLKID_GIC				53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CLKID_AO_MEDIA_CPU			54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CLKID_AO_AHB_SRAM			55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CLKID_AO_AHB_BUS			56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CLKID_AO_IFACE				57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLKID_AO_I2C				58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CLKID_SD_EMMC_B_CLK0			59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CLKID_SD_EMMC_C_CLK0			60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLKID_HIFI_PLL				69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CLKID_PCIE_CML_EN0			79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLKID_PCIE_CML_EN1			80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CLKID_MIPI_ENABLE			81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CLKID_GEN_CLK				84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #endif /* __AXG_CLKC_H */