^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 Baylibre SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Jerome Brunet <jbrunet@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __AXG_AUDIO_CLKC_BINDINGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __AXG_AUDIO_CLKC_BINDINGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define AUD_CLKID_DDR_ARB 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define AUD_CLKID_PDM 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define AUD_CLKID_TDMIN_A 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define AUD_CLKID_TDMIN_B 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define AUD_CLKID_TDMIN_C 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define AUD_CLKID_TDMIN_LB 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AUD_CLKID_TDMOUT_A 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AUD_CLKID_TDMOUT_B 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AUD_CLKID_TDMOUT_C 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AUD_CLKID_FRDDR_A 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AUD_CLKID_FRDDR_B 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AUD_CLKID_FRDDR_C 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AUD_CLKID_TODDR_A 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AUD_CLKID_TODDR_B 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AUD_CLKID_TODDR_C 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AUD_CLKID_LOOPBACK 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AUD_CLKID_SPDIFIN 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AUD_CLKID_SPDIFOUT 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AUD_CLKID_RESAMPLE 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AUD_CLKID_POWER_DETECT 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AUD_CLKID_MST_A_MCLK 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AUD_CLKID_MST_B_MCLK 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AUD_CLKID_MST_C_MCLK 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AUD_CLKID_MST_D_MCLK 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AUD_CLKID_MST_E_MCLK 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AUD_CLKID_MST_F_MCLK 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AUD_CLKID_SPDIFOUT_CLK 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AUD_CLKID_SPDIFIN_CLK 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AUD_CLKID_PDM_DCLK 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AUD_CLKID_PDM_SYSCLK 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AUD_CLKID_MST_A_SCLK 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AUD_CLKID_MST_B_SCLK 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AUD_CLKID_MST_C_SCLK 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AUD_CLKID_MST_D_SCLK 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AUD_CLKID_MST_E_SCLK 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AUD_CLKID_MST_F_SCLK 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AUD_CLKID_MST_A_LRCLK 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AUD_CLKID_MST_B_LRCLK 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AUD_CLKID_MST_C_LRCLK 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AUD_CLKID_MST_D_LRCLK 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AUD_CLKID_MST_E_LRCLK 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AUD_CLKID_MST_F_LRCLK 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AUD_CLKID_TDMIN_A_SCLK_SEL 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AUD_CLKID_TDMIN_B_SCLK_SEL 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AUD_CLKID_TDMIN_C_SCLK_SEL 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AUD_CLKID_TDMIN_LB_SCLK_SEL 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AUD_CLKID_TDMOUT_A_SCLK_SEL 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AUD_CLKID_TDMOUT_B_SCLK_SEL 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AUD_CLKID_TDMOUT_C_SCLK_SEL 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AUD_CLKID_TDMIN_A_SCLK 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AUD_CLKID_TDMIN_B_SCLK 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AUD_CLKID_TDMIN_C_SCLK 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AUD_CLKID_TDMIN_LB_SCLK 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AUD_CLKID_TDMOUT_A_SCLK 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AUD_CLKID_TDMOUT_B_SCLK 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AUD_CLKID_TDMOUT_C_SCLK 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AUD_CLKID_TDMIN_A_LRCLK 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AUD_CLKID_TDMIN_B_LRCLK 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AUD_CLKID_TDMIN_C_LRCLK 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AUD_CLKID_TDMIN_LB_LRCLK 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AUD_CLKID_TDMOUT_A_LRCLK 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AUD_CLKID_TDMOUT_B_LRCLK 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AUD_CLKID_TDMOUT_C_LRCLK 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AUD_CLKID_SPDIFOUT_B 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AUD_CLKID_SPDIFOUT_B_CLK 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AUD_CLKID_TDM_MCLK_PAD0 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AUD_CLKID_TDM_MCLK_PAD1 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AUD_CLKID_TDM_LRCLK_PAD0 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AUD_CLKID_TDM_LRCLK_PAD1 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AUD_CLKID_TDM_LRCLK_PAD2 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AUD_CLKID_TDM_SCLK_PAD0 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AUD_CLKID_TDM_SCLK_PAD1 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AUD_CLKID_TDM_SCLK_PAD2 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AUD_CLKID_TOP 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AUD_CLKID_TORAM 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AUD_CLKID_EQDRC 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AUD_CLKID_RESAMPLE_B 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AUD_CLKID_TOVAD 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AUD_CLKID_LOCKER 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AUD_CLKID_SPDIFIN_LB 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AUD_CLKID_FRDDR_D 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AUD_CLKID_TODDR_D 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AUD_CLKID_LOOPBACK_B 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags