^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014, 2016 Antony Pavlov <antonynpavlov@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __DT_BINDINGS_ATH79_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __DT_BINDINGS_ATH79_CLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define ATH79_CLK_CPU 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define ATH79_CLK_DDR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ATH79_CLK_AHB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ATH79_CLK_REF 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ATH79_CLK_MDIO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ATH79_CLK_END 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #endif /* __DT_BINDINGS_ATH79_CLK_H */