Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This header provides constants for AT91 pmc status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * The constants defined in this header are being used in dts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _DT_BINDINGS_CLK_AT91_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _DT_BINDINGS_CLK_AT91_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PMC_TYPE_CORE		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PMC_TYPE_SYSTEM		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PMC_TYPE_PERIPHERAL	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PMC_TYPE_GCK		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PMC_TYPE_PROGRAMMABLE	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PMC_SLOW		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PMC_MCK			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PMC_UTMI		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PMC_MAIN		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PMC_MCK2		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PMC_I2S0_MUX		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PMC_I2S1_MUX		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PMC_PLLACK		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PMC_PLLBCK		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PMC_AUDIOPLLCK		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #ifndef AT91_PMC_MOSCS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AT91_PMC_MOSCS		0		/* MOSCS Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AT91_PMC_LOCKA		1		/* PLLA Lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AT91_PMC_LOCKB		2		/* PLLB Lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AT91_PMC_MCKRDY		3		/* Master Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AT91_PMC_LOCKU		6		/* UPLL Lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AT91_PMC_PCKRDY(id)	(8 + (id))	/* Programmable Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AT91_PMC_MOSCSELS	16		/* Main Oscillator Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AT91_PMC_MOSCRCS	17		/* Main On-Chip RC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AT91_PMC_CFDEV		18		/* Clock Failure Detector Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AT91_PMC_GCKRDY		24		/* Generated Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #endif