^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef DT_BINDINGS_AST2600_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define DT_BINDINGS_AST2600_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define ASPEED_CLK_GATE_ECLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define ASPEED_CLK_GATE_GCLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define ASPEED_CLK_GATE_MCLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define ASPEED_CLK_GATE_VCLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ASPEED_CLK_GATE_BCLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ASPEED_CLK_GATE_DCLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define ASPEED_CLK_GATE_LCLK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ASPEED_CLK_GATE_LHCCLK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ASPEED_CLK_GATE_D1CLK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ASPEED_CLK_GATE_YCLK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ASPEED_CLK_GATE_REF0CLK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ASPEED_CLK_GATE_REF1CLK 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ASPEED_CLK_GATE_ESPICLK 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ASPEED_CLK_GATE_USBUHCICLK 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ASPEED_CLK_GATE_USBPORT1CLK 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ASPEED_CLK_GATE_USBPORT2CLK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ASPEED_CLK_GATE_RSACLK 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ASPEED_CLK_GATE_RVASCLK 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ASPEED_CLK_GATE_MAC1CLK 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ASPEED_CLK_GATE_MAC2CLK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ASPEED_CLK_GATE_MAC3CLK 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ASPEED_CLK_GATE_MAC4CLK 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ASPEED_CLK_GATE_UART1CLK 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ASPEED_CLK_GATE_UART2CLK 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ASPEED_CLK_GATE_UART3CLK 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ASPEED_CLK_GATE_UART4CLK 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ASPEED_CLK_GATE_UART5CLK 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ASPEED_CLK_GATE_UART6CLK 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ASPEED_CLK_GATE_UART7CLK 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ASPEED_CLK_GATE_UART8CLK 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ASPEED_CLK_GATE_UART9CLK 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ASPEED_CLK_GATE_UART10CLK 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ASPEED_CLK_GATE_UART11CLK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ASPEED_CLK_GATE_UART12CLK 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ASPEED_CLK_GATE_UART13CLK 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ASPEED_CLK_GATE_SDCLK 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ASPEED_CLK_GATE_EMMCCLK 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ASPEED_CLK_GATE_I3C0CLK 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ASPEED_CLK_GATE_I3C1CLK 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ASPEED_CLK_GATE_I3C2CLK 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ASPEED_CLK_GATE_I3C3CLK 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ASPEED_CLK_GATE_I3C4CLK 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ASPEED_CLK_GATE_I3C5CLK 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ASPEED_CLK_GATE_I3C6CLK 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ASPEED_CLK_GATE_I3C7CLK 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ASPEED_CLK_GATE_FSICLK 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ASPEED_CLK_HPLL 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ASPEED_CLK_MPLL 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ASPEED_CLK_DPLL 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ASPEED_CLK_EPLL 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ASPEED_CLK_APLL 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ASPEED_CLK_AHB 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ASPEED_CLK_APB1 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ASPEED_CLK_APB2 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ASPEED_CLK_BCLK 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ASPEED_CLK_D1CLK 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ASPEED_CLK_VCLK 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ASPEED_CLK_LHCLK 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ASPEED_CLK_UART 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ASPEED_CLK_UARTX 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ASPEED_CLK_SDIO 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ASPEED_CLK_EMMC 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ASPEED_CLK_ECLK 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ASPEED_CLK_ECLK_MUX 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ASPEED_CLK_MAC12 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ASPEED_CLK_MAC34 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ASPEED_CLK_USBPHY_40M 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ASPEED_CLK_MAC1RCLK 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ASPEED_CLK_MAC2RCLK 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ASPEED_CLK_MAC3RCLK 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ASPEED_CLK_MAC4RCLK 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Only list resets here that are not part of a gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ASPEED_RESET_ADC 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ASPEED_RESET_JTAG_MASTER2 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ASPEED_RESET_I3C_DMA 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ASPEED_RESET_PWM 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ASPEED_RESET_PECI 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ASPEED_RESET_MII 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ASPEED_RESET_I2C 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ASPEED_RESET_H2X 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ASPEED_RESET_GP_MCU 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ASPEED_RESET_DP_MCU 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ASPEED_RESET_DP 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ASPEED_RESET_RC_XDMA 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ASPEED_RESET_GRAPHICS 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ASPEED_RESET_DEV_XDMA 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ASPEED_RESET_DEV_MCTP 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ASPEED_RESET_RC_MCTP 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ASPEED_RESET_JTAG_MASTER 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ASPEED_RESET_PCIE_DEV_O 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ASPEED_RESET_PCIE_DEV_OEN 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ASPEED_RESET_PCIE_RC_O 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ASPEED_RESET_PCIE_RC_OEN 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ASPEED_RESET_PCI_DP 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ASPEED_RESET_AHB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ASPEED_RESET_SDRAM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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