Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #ifndef DT_BINDINGS_ASPEED_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #define DT_BINDINGS_ASPEED_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define ASPEED_CLK_GATE_ECLK		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define ASPEED_CLK_GATE_GCLK		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define ASPEED_CLK_GATE_MCLK		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define ASPEED_CLK_GATE_VCLK		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define ASPEED_CLK_GATE_BCLK		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ASPEED_CLK_GATE_DCLK		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ASPEED_CLK_GATE_REFCLK		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ASPEED_CLK_GATE_USBPORT2CLK	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define ASPEED_CLK_GATE_LCLK		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ASPEED_CLK_GATE_USBUHCICLK	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ASPEED_CLK_GATE_D1CLK		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ASPEED_CLK_GATE_YCLK		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ASPEED_CLK_GATE_USBPORT1CLK	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ASPEED_CLK_GATE_UART1CLK	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ASPEED_CLK_GATE_UART2CLK	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ASPEED_CLK_GATE_UART5CLK	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ASPEED_CLK_GATE_ESPICLK		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ASPEED_CLK_GATE_MAC1CLK		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ASPEED_CLK_GATE_MAC2CLK		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ASPEED_CLK_GATE_RSACLK		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ASPEED_CLK_GATE_UART3CLK	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ASPEED_CLK_GATE_UART4CLK	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ASPEED_CLK_GATE_SDCLK		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ASPEED_CLK_GATE_LHCCLK		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ASPEED_CLK_HPLL			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ASPEED_CLK_AHB			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ASPEED_CLK_APB			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ASPEED_CLK_UART			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ASPEED_CLK_SDIO			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ASPEED_CLK_ECLK			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ASPEED_CLK_ECLK_MUX		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ASPEED_CLK_LHCLK		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ASPEED_CLK_MAC			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ASPEED_CLK_BCLK			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ASPEED_CLK_MPLL			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ASPEED_CLK_24M			35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ASPEED_CLK_MAC1RCLK		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ASPEED_CLK_MAC2RCLK		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ASPEED_RESET_XDMA		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ASPEED_RESET_MCTP		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ASPEED_RESET_ADC		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ASPEED_RESET_JTAG_MASTER	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ASPEED_RESET_MIC		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ASPEED_RESET_PWM		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ASPEED_RESET_PECI		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ASPEED_RESET_I2C		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ASPEED_RESET_AHB		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ASPEED_RESET_CRT1		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif