Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2017 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #ifndef __DT_BINDINGS_CLK_AM4_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define __DT_BINDINGS_CLK_AM4_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define AM4_CLKCTRL_OFFSET	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define AM4_CLKCTRL_INDEX(offset)	((offset) - AM4_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /* l4_wkup clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define AM4_ADC_TSC_CLKCTRL	AM4_CLKCTRL_INDEX(0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define AM4_L4_WKUP_CLKCTRL	AM4_CLKCTRL_INDEX(0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define AM4_WKUP_M3_CLKCTRL	AM4_CLKCTRL_INDEX(0x228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define AM4_COUNTER_32K_CLKCTRL	AM4_CLKCTRL_INDEX(0x230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define AM4_TIMER1_CLKCTRL	AM4_CLKCTRL_INDEX(0x328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define AM4_WD_TIMER2_CLKCTRL	AM4_CLKCTRL_INDEX(0x338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define AM4_I2C1_CLKCTRL	AM4_CLKCTRL_INDEX(0x340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define AM4_UART1_CLKCTRL	AM4_CLKCTRL_INDEX(0x348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define AM4_SMARTREFLEX0_CLKCTRL	AM4_CLKCTRL_INDEX(0x350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AM4_SMARTREFLEX1_CLKCTRL	AM4_CLKCTRL_INDEX(0x358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AM4_CONTROL_CLKCTRL	AM4_CLKCTRL_INDEX(0x360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AM4_GPIO1_CLKCTRL	AM4_CLKCTRL_INDEX(0x368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* mpu clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AM4_MPU_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* gfx_l3 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AM4_GFX_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* l4_rtc clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define AM4_RTC_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* l4_per clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define AM4_L3_MAIN_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define AM4_AES_CLKCTRL	AM4_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define AM4_DES_CLKCTRL	AM4_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define AM4_L3_INSTR_CLKCTRL	AM4_CLKCTRL_INDEX(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define AM4_OCMCRAM_CLKCTRL	AM4_CLKCTRL_INDEX(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define AM4_SHAM_CLKCTRL	AM4_CLKCTRL_INDEX(0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define AM4_VPFE0_CLKCTRL	AM4_CLKCTRL_INDEX(0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define AM4_VPFE1_CLKCTRL	AM4_CLKCTRL_INDEX(0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define AM4_TPCC_CLKCTRL	AM4_CLKCTRL_INDEX(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define AM4_TPTC0_CLKCTRL	AM4_CLKCTRL_INDEX(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define AM4_TPTC1_CLKCTRL	AM4_CLKCTRL_INDEX(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define AM4_TPTC2_CLKCTRL	AM4_CLKCTRL_INDEX(0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define AM4_L4_HS_CLKCTRL	AM4_CLKCTRL_INDEX(0xa0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define AM4_GPMC_CLKCTRL	AM4_CLKCTRL_INDEX(0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define AM4_MCASP0_CLKCTRL	AM4_CLKCTRL_INDEX(0x238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define AM4_MCASP1_CLKCTRL	AM4_CLKCTRL_INDEX(0x240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define AM4_MMC3_CLKCTRL	AM4_CLKCTRL_INDEX(0x248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define AM4_QSPI_CLKCTRL	AM4_CLKCTRL_INDEX(0x258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define AM4_USB_OTG_SS0_CLKCTRL	AM4_CLKCTRL_INDEX(0x260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define AM4_USB_OTG_SS1_CLKCTRL	AM4_CLKCTRL_INDEX(0x268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define AM4_PRUSS_CLKCTRL	AM4_CLKCTRL_INDEX(0x320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define AM4_L4_LS_CLKCTRL	AM4_CLKCTRL_INDEX(0x420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define AM4_D_CAN0_CLKCTRL	AM4_CLKCTRL_INDEX(0x428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define AM4_D_CAN1_CLKCTRL	AM4_CLKCTRL_INDEX(0x430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define AM4_EPWMSS0_CLKCTRL	AM4_CLKCTRL_INDEX(0x438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define AM4_EPWMSS1_CLKCTRL	AM4_CLKCTRL_INDEX(0x440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define AM4_EPWMSS2_CLKCTRL	AM4_CLKCTRL_INDEX(0x448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define AM4_EPWMSS3_CLKCTRL	AM4_CLKCTRL_INDEX(0x450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define AM4_EPWMSS4_CLKCTRL	AM4_CLKCTRL_INDEX(0x458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define AM4_EPWMSS5_CLKCTRL	AM4_CLKCTRL_INDEX(0x460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define AM4_ELM_CLKCTRL	AM4_CLKCTRL_INDEX(0x468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define AM4_GPIO2_CLKCTRL	AM4_CLKCTRL_INDEX(0x478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define AM4_GPIO3_CLKCTRL	AM4_CLKCTRL_INDEX(0x480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define AM4_GPIO4_CLKCTRL	AM4_CLKCTRL_INDEX(0x488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define AM4_GPIO5_CLKCTRL	AM4_CLKCTRL_INDEX(0x490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define AM4_GPIO6_CLKCTRL	AM4_CLKCTRL_INDEX(0x498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define AM4_HDQ1W_CLKCTRL	AM4_CLKCTRL_INDEX(0x4a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define AM4_I2C2_CLKCTRL	AM4_CLKCTRL_INDEX(0x4a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define AM4_I2C3_CLKCTRL	AM4_CLKCTRL_INDEX(0x4b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define AM4_MAILBOX_CLKCTRL	AM4_CLKCTRL_INDEX(0x4b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define AM4_MMC1_CLKCTRL	AM4_CLKCTRL_INDEX(0x4c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define AM4_MMC2_CLKCTRL	AM4_CLKCTRL_INDEX(0x4c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define AM4_RNG_CLKCTRL	AM4_CLKCTRL_INDEX(0x4e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define AM4_SPI0_CLKCTRL	AM4_CLKCTRL_INDEX(0x500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define AM4_SPI1_CLKCTRL	AM4_CLKCTRL_INDEX(0x508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define AM4_SPI2_CLKCTRL	AM4_CLKCTRL_INDEX(0x510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define AM4_SPI3_CLKCTRL	AM4_CLKCTRL_INDEX(0x518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define AM4_SPI4_CLKCTRL	AM4_CLKCTRL_INDEX(0x520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define AM4_SPINLOCK_CLKCTRL	AM4_CLKCTRL_INDEX(0x528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define AM4_TIMER2_CLKCTRL	AM4_CLKCTRL_INDEX(0x530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define AM4_TIMER3_CLKCTRL	AM4_CLKCTRL_INDEX(0x538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define AM4_TIMER4_CLKCTRL	AM4_CLKCTRL_INDEX(0x540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define AM4_TIMER5_CLKCTRL	AM4_CLKCTRL_INDEX(0x548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define AM4_TIMER6_CLKCTRL	AM4_CLKCTRL_INDEX(0x550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define AM4_TIMER7_CLKCTRL	AM4_CLKCTRL_INDEX(0x558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define AM4_TIMER8_CLKCTRL	AM4_CLKCTRL_INDEX(0x560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define AM4_TIMER9_CLKCTRL	AM4_CLKCTRL_INDEX(0x568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define AM4_TIMER10_CLKCTRL	AM4_CLKCTRL_INDEX(0x570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define AM4_TIMER11_CLKCTRL	AM4_CLKCTRL_INDEX(0x578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define AM4_UART2_CLKCTRL	AM4_CLKCTRL_INDEX(0x580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define AM4_UART3_CLKCTRL	AM4_CLKCTRL_INDEX(0x588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define AM4_UART4_CLKCTRL	AM4_CLKCTRL_INDEX(0x590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define AM4_UART5_CLKCTRL	AM4_CLKCTRL_INDEX(0x598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AM4_UART6_CLKCTRL	AM4_CLKCTRL_INDEX(0x5a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AM4_OCP2SCP0_CLKCTRL	AM4_CLKCTRL_INDEX(0x5b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AM4_OCP2SCP1_CLKCTRL	AM4_CLKCTRL_INDEX(0x5c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AM4_EMIF_CLKCTRL	AM4_CLKCTRL_INDEX(0x720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AM4_DSS_CORE_CLKCTRL	AM4_CLKCTRL_INDEX(0xa20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AM4_CPGMAC0_CLKCTRL	AM4_CLKCTRL_INDEX(0xb20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* XXX: Compatibility part end. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* l3s_tsc clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AM4_L3S_TSC_CLKCTRL_OFFSET	0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AM4_L3S_TSC_CLKCTRL_INDEX(offset)	((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AM4_L3S_TSC_ADC_TSC_CLKCTRL	AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* l4_wkup_aon clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET	0x228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AM4_L4_WKUP_AON_CLKCTRL_INDEX(offset)	((offset) - AM4_L4_WKUP_AON_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL	AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL	AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* l4_wkup clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AM4_L4_WKUP_CLKCTRL_OFFSET	0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AM4_L4_WKUP_CLKCTRL_INDEX(offset)	((offset) - AM4_L4_WKUP_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AM4_L4_WKUP_L4_WKUP_CLKCTRL	AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AM4_L4_WKUP_TIMER1_CLKCTRL	AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL	AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AM4_L4_WKUP_I2C1_CLKCTRL	AM4_L4_WKUP_CLKCTRL_INDEX(0x340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define AM4_L4_WKUP_UART1_CLKCTRL	AM4_L4_WKUP_CLKCTRL_INDEX(0x348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL	AM4_L4_WKUP_CLKCTRL_INDEX(0x350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL	AM4_L4_WKUP_CLKCTRL_INDEX(0x358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define AM4_L4_WKUP_CONTROL_CLKCTRL	AM4_L4_WKUP_CLKCTRL_INDEX(0x360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define AM4_L4_WKUP_GPIO1_CLKCTRL	AM4_L4_WKUP_CLKCTRL_INDEX(0x368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* mpu clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AM4_MPU_MPU_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* gfx_l3 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define AM4_GFX_L3_GFX_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* l4_rtc clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AM4_L4_RTC_RTC_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* l3 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define AM4_L3_L3_MAIN_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AM4_L3_AES_CLKCTRL	AM4_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define AM4_L3_DES_CLKCTRL	AM4_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define AM4_L3_L3_INSTR_CLKCTRL	AM4_CLKCTRL_INDEX(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define AM4_L3_OCMCRAM_CLKCTRL	AM4_CLKCTRL_INDEX(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define AM4_L3_SHAM_CLKCTRL	AM4_CLKCTRL_INDEX(0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AM4_L3_TPCC_CLKCTRL	AM4_CLKCTRL_INDEX(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AM4_L3_TPTC0_CLKCTRL	AM4_CLKCTRL_INDEX(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AM4_L3_TPTC1_CLKCTRL	AM4_CLKCTRL_INDEX(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define AM4_L3_TPTC2_CLKCTRL	AM4_CLKCTRL_INDEX(0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define AM4_L3_L4_HS_CLKCTRL	AM4_CLKCTRL_INDEX(0xa0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* l3s clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define AM4_L3S_CLKCTRL_OFFSET	0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define AM4_L3S_CLKCTRL_INDEX(offset)	((offset) - AM4_L3S_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define AM4_L3S_VPFE0_CLKCTRL	AM4_L3S_CLKCTRL_INDEX(0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define AM4_L3S_VPFE1_CLKCTRL	AM4_L3S_CLKCTRL_INDEX(0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define AM4_L3S_GPMC_CLKCTRL	AM4_L3S_CLKCTRL_INDEX(0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define AM4_L3S_MCASP0_CLKCTRL	AM4_L3S_CLKCTRL_INDEX(0x238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define AM4_L3S_MCASP1_CLKCTRL	AM4_L3S_CLKCTRL_INDEX(0x240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define AM4_L3S_MMC3_CLKCTRL	AM4_L3S_CLKCTRL_INDEX(0x248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define AM4_L3S_QSPI_CLKCTRL	AM4_L3S_CLKCTRL_INDEX(0x258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define AM4_L3S_USB_OTG_SS0_CLKCTRL	AM4_L3S_CLKCTRL_INDEX(0x260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define AM4_L3S_USB_OTG_SS1_CLKCTRL	AM4_L3S_CLKCTRL_INDEX(0x268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* pruss_ocp clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define AM4_PRUSS_OCP_CLKCTRL_OFFSET	0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define AM4_PRUSS_OCP_CLKCTRL_INDEX(offset)	((offset) - AM4_PRUSS_OCP_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define AM4_PRUSS_OCP_PRUSS_CLKCTRL	AM4_PRUSS_OCP_CLKCTRL_INDEX(0x320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* l4ls clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define AM4_L4LS_CLKCTRL_OFFSET	0x420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define AM4_L4LS_CLKCTRL_INDEX(offset)	((offset) - AM4_L4LS_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define AM4_L4LS_L4_LS_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define AM4_L4LS_D_CAN0_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define AM4_L4LS_D_CAN1_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define AM4_L4LS_EPWMSS0_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define AM4_L4LS_EPWMSS1_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define AM4_L4LS_EPWMSS2_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define AM4_L4LS_EPWMSS3_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define AM4_L4LS_EPWMSS4_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define AM4_L4LS_EPWMSS5_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define AM4_L4LS_ELM_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define AM4_L4LS_GPIO2_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define AM4_L4LS_GPIO3_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define AM4_L4LS_GPIO4_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define AM4_L4LS_GPIO5_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define AM4_L4LS_GPIO6_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AM4_L4LS_HDQ1W_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x4a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define AM4_L4LS_I2C2_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x4a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define AM4_L4LS_I2C3_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x4b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define AM4_L4LS_MAILBOX_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x4b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define AM4_L4LS_MMC1_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x4c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define AM4_L4LS_MMC2_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x4c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define AM4_L4LS_RNG_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x4e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define AM4_L4LS_SPI0_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define AM4_L4LS_SPI1_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define AM4_L4LS_SPI2_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define AM4_L4LS_SPI3_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define AM4_L4LS_SPI4_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define AM4_L4LS_SPINLOCK_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define AM4_L4LS_TIMER2_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define AM4_L4LS_TIMER3_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define AM4_L4LS_TIMER4_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define AM4_L4LS_TIMER5_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define AM4_L4LS_TIMER6_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define AM4_L4LS_TIMER7_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define AM4_L4LS_TIMER8_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define AM4_L4LS_TIMER9_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define AM4_L4LS_TIMER10_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define AM4_L4LS_TIMER11_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define AM4_L4LS_UART2_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define AM4_L4LS_UART3_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define AM4_L4LS_UART4_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define AM4_L4LS_UART5_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define AM4_L4LS_UART6_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x5a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define AM4_L4LS_OCP2SCP0_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x5b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define AM4_L4LS_OCP2SCP1_CLKCTRL	AM4_L4LS_CLKCTRL_INDEX(0x5c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* emif clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define AM4_EMIF_CLKCTRL_OFFSET	0x720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define AM4_EMIF_CLKCTRL_INDEX(offset)	((offset) - AM4_EMIF_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define AM4_EMIF_EMIF_CLKCTRL	AM4_EMIF_CLKCTRL_INDEX(0x720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* dss clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define AM4_DSS_CLKCTRL_OFFSET	0xa20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define AM4_DSS_CLKCTRL_INDEX(offset)	((offset) - AM4_DSS_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define AM4_DSS_DSS_CORE_CLKCTRL	AM4_DSS_CLKCTRL_INDEX(0xa20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* cpsw_125mhz clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define AM4_CPSW_125MHZ_CLKCTRL_OFFSET	0xb20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define AM4_CPSW_125MHZ_CLKCTRL_INDEX(offset)	((offset) - AM4_CPSW_125MHZ_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL	AM4_CPSW_125MHZ_CLKCTRL_INDEX(0xb20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #endif