Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2017 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #ifndef __DT_BINDINGS_CLK_AM3_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define __DT_BINDINGS_CLK_AM3_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define AM3_CLKCTRL_OFFSET	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define AM3_CLKCTRL_INDEX(offset)	((offset) - AM3_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /* l4_per clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define AM3_L4_PER_CLKCTRL_OFFSET	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define AM3_L4_PER_CLKCTRL_INDEX(offset)	((offset) - AM3_L4_PER_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define AM3_CPGMAC0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define AM3_LCDC_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define AM3_USB_OTG_HS_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define AM3_TPTC0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define AM3_EMIF_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define AM3_OCMCRAM_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define AM3_GPMC_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AM3_MCASP0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AM3_UART6_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AM3_MMC1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x3c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AM3_ELM_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AM3_I2C3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AM3_I2C2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define AM3_SPI0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x4c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define AM3_SPI1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AM3_L4_LS_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define AM3_MCASP1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AM3_UART2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x6c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define AM3_UART3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define AM3_UART4_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define AM3_UART5_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define AM3_TIMER7_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x7c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define AM3_TIMER2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define AM3_TIMER3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define AM3_TIMER4_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define AM3_RNG_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define AM3_AES_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define AM3_SHAM_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xa0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define AM3_GPIO2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define AM3_GPIO3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xb0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define AM3_GPIO4_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xb4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define AM3_TPCC_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xbc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define AM3_D_CAN0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define AM3_D_CAN1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xc4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define AM3_EPWMSS1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define AM3_EPWMSS0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xd4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define AM3_EPWMSS2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xd8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define AM3_L3_INSTR_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xdc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define AM3_L3_MAIN_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xe0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define AM3_PRUSS_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xe8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define AM3_TIMER5_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define AM3_TIMER6_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xf0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define AM3_MMC2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xf4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define AM3_MMC3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xf8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define AM3_TPTC1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xfc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define AM3_TPTC2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define AM3_SPINLOCK_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x10c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define AM3_MAILBOX_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define AM3_L4_HS_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define AM3_OCPWP_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define AM3_CLKDIV32K_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x14c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /* l4_wkup clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define AM3_L4_WKUP_CLKCTRL_OFFSET	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define AM3_L4_WKUP_CLKCTRL_INDEX(offset)	((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define AM3_CONTROL_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define AM3_GPIO1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define AM3_L4_WKUP_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define AM3_DEBUGSS_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define AM3_WKUP_M3_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xb0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define AM3_UART1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xb4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define AM3_I2C1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xb8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define AM3_ADC_TSC_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xbc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define AM3_SMARTREFLEX0_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define AM3_TIMER1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xc4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define AM3_SMARTREFLEX1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xc8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define AM3_WD_TIMER2_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xd4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /* mpu clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define AM3_MPU_CLKCTRL_OFFSET	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define AM3_MPU_CLKCTRL_INDEX(offset)	((offset) - AM3_MPU_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define AM3_MPU_CLKCTRL	AM3_MPU_CLKCTRL_INDEX(0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /* l4_rtc clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define AM3_RTC_CLKCTRL	AM3_CLKCTRL_INDEX(0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /* gfx_l3 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define AM3_GFX_L3_CLKCTRL_OFFSET	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define AM3_GFX_L3_CLKCTRL_INDEX(offset)	((offset) - AM3_GFX_L3_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define AM3_GFX_CLKCTRL	AM3_GFX_L3_CLKCTRL_INDEX(0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /* l4_cefuse clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define AM3_L4_CEFUSE_CLKCTRL_OFFSET	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset)	((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AM3_CEFUSE_CLKCTRL	AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* XXX: Compatibility part end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* l4ls clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AM3_L4LS_CLKCTRL_OFFSET	0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AM3_L4LS_CLKCTRL_INDEX(offset)	((offset) - AM3_L4LS_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AM3_L4LS_UART6_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AM3_L4LS_MMC1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x3c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AM3_L4LS_ELM_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AM3_L4LS_I2C3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AM3_L4LS_I2C2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AM3_L4LS_SPI0_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x4c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AM3_L4LS_SPI1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AM3_L4LS_L4_LS_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AM3_L4LS_UART2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x6c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AM3_L4LS_UART3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AM3_L4LS_UART4_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AM3_L4LS_UART5_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AM3_L4LS_TIMER7_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x7c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AM3_L4LS_TIMER2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AM3_L4LS_TIMER3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AM3_L4LS_TIMER4_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AM3_L4LS_RNG_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AM3_L4LS_GPIO2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AM3_L4LS_GPIO3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xb0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AM3_L4LS_GPIO4_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xb4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define AM3_L4LS_D_CAN0_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AM3_L4LS_D_CAN1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xc4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AM3_L4LS_EPWMSS1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define AM3_L4LS_EPWMSS0_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xd4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define AM3_L4LS_EPWMSS2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xd8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AM3_L4LS_TIMER5_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AM3_L4LS_TIMER6_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xf0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AM3_L4LS_MMC2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xf4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AM3_L4LS_SPINLOCK_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x10c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AM3_L4LS_MAILBOX_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define AM3_L4LS_OCPWP_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* l3s clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AM3_L3S_CLKCTRL_OFFSET	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AM3_L3S_CLKCTRL_INDEX(offset)	((offset) - AM3_L3S_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AM3_L3S_USB_OTG_HS_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define AM3_L3S_GPMC_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AM3_L3S_MCASP0_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define AM3_L3S_MCASP1_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define AM3_L3S_MMC3_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0xf8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* l3 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AM3_L3_CLKCTRL_OFFSET	0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AM3_L3_CLKCTRL_INDEX(offset)	((offset) - AM3_L3_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AM3_L3_TPTC0_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define AM3_L3_EMIF_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define AM3_L3_OCMCRAM_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define AM3_L3_AES_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define AM3_L3_SHAM_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xa0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define AM3_L3_TPCC_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xbc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define AM3_L3_L3_INSTR_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xdc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define AM3_L3_L3_MAIN_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xe0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define AM3_L3_TPTC1_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xfc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define AM3_L3_TPTC2_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* l4hs clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define AM3_L4HS_CLKCTRL_OFFSET	0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define AM3_L4HS_CLKCTRL_INDEX(offset)	((offset) - AM3_L4HS_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define AM3_L4HS_L4_HS_CLKCTRL	AM3_L4HS_CLKCTRL_INDEX(0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* pruss_ocp clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define AM3_PRUSS_OCP_CLKCTRL_OFFSET	0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset)	((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define AM3_PRUSS_OCP_PRUSS_CLKCTRL	AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* cpsw_125mhz clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL	AM3_CLKCTRL_INDEX(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* lcdc clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define AM3_LCDC_CLKCTRL_OFFSET	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define AM3_LCDC_CLKCTRL_INDEX(offset)	((offset) - AM3_LCDC_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define AM3_LCDC_LCDC_CLKCTRL	AM3_LCDC_CLKCTRL_INDEX(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* clk_24mhz clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define AM3_CLK_24MHZ_CLKCTRL_OFFSET	0x14c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset)	((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL	AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* l4_wkup clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define AM3_L4_WKUP_CONTROL_CLKCTRL	AM3_CLKCTRL_INDEX(0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define AM3_L4_WKUP_GPIO1_CLKCTRL	AM3_CLKCTRL_INDEX(0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define AM3_L4_WKUP_L4_WKUP_CLKCTRL	AM3_CLKCTRL_INDEX(0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define AM3_L4_WKUP_UART1_CLKCTRL	AM3_CLKCTRL_INDEX(0xb4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define AM3_L4_WKUP_I2C1_CLKCTRL	AM3_CLKCTRL_INDEX(0xb8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AM3_L4_WKUP_ADC_TSC_CLKCTRL	AM3_CLKCTRL_INDEX(0xbc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL	AM3_CLKCTRL_INDEX(0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define AM3_L4_WKUP_TIMER1_CLKCTRL	AM3_CLKCTRL_INDEX(0xc4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL	AM3_CLKCTRL_INDEX(0xc8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define AM3_L4_WKUP_WD_TIMER2_CLKCTRL	AM3_CLKCTRL_INDEX(0xd4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* l3_aon clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define AM3_L3_AON_CLKCTRL_OFFSET	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define AM3_L3_AON_CLKCTRL_INDEX(offset)	((offset) - AM3_L3_AON_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define AM3_L3_AON_DEBUGSS_CLKCTRL	AM3_L3_AON_CLKCTRL_INDEX(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* l4_wkup_aon clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define AM3_L4_WKUP_AON_CLKCTRL_OFFSET	0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset)	((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL	AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* mpu clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define AM3_MPU_MPU_CLKCTRL	AM3_CLKCTRL_INDEX(0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* l4_rtc clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define AM3_L4_RTC_RTC_CLKCTRL	AM3_CLKCTRL_INDEX(0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* gfx_l3 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define AM3_GFX_L3_GFX_CLKCTRL	AM3_CLKCTRL_INDEX(0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* l4_cefuse clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define AM3_L4_CEFUSE_CEFUSE_CLKCTRL	AM3_CLKCTRL_INDEX(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #endif