^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_CLK_ASM9260_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_CLK_ASM9260_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* ahb gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CLKID_AHB_ROM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CLKID_AHB_RAM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CLKID_AHB_GPIO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLKID_AHB_MAC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLKID_AHB_EMI 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLKID_AHB_USB0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLKID_AHB_USB1 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLKID_AHB_DMA0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLKID_AHB_DMA1 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLKID_AHB_UART0 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLKID_AHB_UART1 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLKID_AHB_UART2 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLKID_AHB_UART3 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLKID_AHB_UART4 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLKID_AHB_UART5 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLKID_AHB_UART6 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLKID_AHB_UART7 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLKID_AHB_UART8 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLKID_AHB_UART9 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLKID_AHB_I2S0 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLKID_AHB_I2C0 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLKID_AHB_I2C1 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLKID_AHB_SSP0 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLKID_AHB_IOCONFIG 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLKID_AHB_WDT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLKID_AHB_CAN0 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLKID_AHB_CAN1 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLKID_AHB_MPWM 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLKID_AHB_SPI0 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLKID_AHB_SPI1 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLKID_AHB_QEI 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLKID_AHB_QUADSPI0 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLKID_AHB_CAMIF 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLKID_AHB_LCDIF 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLKID_AHB_TIMER0 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLKID_AHB_TIMER1 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLKID_AHB_TIMER2 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLKID_AHB_TIMER3 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLKID_AHB_IRQ 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLKID_AHB_RTC 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLKID_AHB_NAND 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLKID_AHB_ADC0 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLKID_AHB_LED 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLKID_AHB_DAC0 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLKID_AHB_LCD 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLKID_AHB_I2S1 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLKID_AHB_MAC1 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* devider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLKID_SYS_CPU 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLKID_SYS_AHB 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLKID_SYS_I2S0M 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLKID_SYS_I2S0S 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CLKID_SYS_I2S1M 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CLKID_SYS_I2S1S 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CLKID_SYS_UART0 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CLKID_SYS_UART1 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLKID_SYS_UART2 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CLKID_SYS_UART3 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CLKID_SYS_UART4 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLKID_SYS_UART5 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CLKID_SYS_UART6 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLKID_SYS_UART7 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CLKID_SYS_UART8 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CLKID_SYS_UART9 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CLKID_SYS_SPI0 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CLKID_SYS_SPI1 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CLKID_SYS_QUADSPI 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CLKID_SYS_SSP0 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CLKID_SYS_NAND 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CLKID_SYS_TRACE 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CLKID_SYS_CAMM 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CLKID_SYS_WDT 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CLKID_SYS_CLKOUT 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CLKID_SYS_MAC 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CLKID_SYS_LCD 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CLKID_SYS_ADCANA 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MAX_CLKS 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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