^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2019, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __AGILEX_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __AGILEX_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* fixed rate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define AGILEX_OSC1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define AGILEX_CB_INTOSC_HS_DIV2_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define AGILEX_CB_INTOSC_LS_CLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define AGILEX_L4_SYS_FREE_CLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define AGILEX_F2S_FREE_CLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* PLL clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AGILEX_MAIN_PLL_CLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AGILEX_MAIN_PLL_C0_CLK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AGILEX_MAIN_PLL_C1_CLK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AGILEX_MAIN_PLL_C2_CLK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AGILEX_MAIN_PLL_C3_CLK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AGILEX_PERIPH_PLL_CLK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AGILEX_PERIPH_PLL_C0_CLK 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AGILEX_PERIPH_PLL_C1_CLK 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AGILEX_PERIPH_PLL_C2_CLK 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AGILEX_PERIPH_PLL_C3_CLK 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AGILEX_MPU_FREE_CLK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AGILEX_MPU_CCU_CLK 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AGILEX_BOOT_CLK 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* fixed factor clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AGILEX_L3_MAIN_FREE_CLK 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AGILEX_NOC_FREE_CLK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AGILEX_S2F_USR0_CLK 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AGILEX_NOC_CLK 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AGILEX_EMAC_A_FREE_CLK 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AGILEX_EMAC_B_FREE_CLK 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AGILEX_EMAC_PTP_FREE_CLK 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AGILEX_GPIO_DB_FREE_CLK 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AGILEX_SDMMC_FREE_CLK 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AGILEX_S2F_USER0_FREE_CLK 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AGILEX_S2F_USER1_FREE_CLK 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AGILEX_PSI_REF_FREE_CLK 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Gate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AGILEX_MPU_CLK 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AGILEX_MPU_L2RAM_CLK 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AGILEX_MPU_PERIPH_CLK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AGILEX_L4_MAIN_CLK 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AGILEX_L4_MP_CLK 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AGILEX_L4_SP_CLK 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AGILEX_CS_AT_CLK 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AGILEX_CS_TRACE_CLK 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AGILEX_CS_PDBG_CLK 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AGILEX_CS_TIMER_CLK 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AGILEX_S2F_USER0_CLK 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AGILEX_EMAC0_CLK 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AGILEX_EMAC1_CLK 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AGILEX_EMAC2_CLK 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AGILEX_EMAC_PTP_CLK 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AGILEX_GPIO_DB_CLK 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AGILEX_NAND_CLK 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AGILEX_PSI_REF_CLK 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AGILEX_S2F_USER1_CLK 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AGILEX_SDMMC_CLK 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AGILEX_SPI_M_CLK 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AGILEX_USB_CLK 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AGILEX_NAND_X_CLK 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AGILEX_NAND_ECC_CLK 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AGILEX_NUM_CLKS 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #endif /* __AGILEX_CLOCK_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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