^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Device Tree binding constants for Actions Semi S900 Clock Management Unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (c) 2014 Actions Semi Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Copyright (c) 2018 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __DT_BINDINGS_CLOCK_S900_CMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __DT_BINDINGS_CLOCK_S900_CMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CLK_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* fixed rate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLK_LOSC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_HOSC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* pll clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_CORE_PLL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_DEV_PLL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_DDR_PLL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_NAND_PLL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_DISPLAY_PLL 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_DSI_PLL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_ASSIST_PLL 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_AUDIO_PLL 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* system clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_CPU 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_DEV 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_NOC 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_NOC_MUX 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_NOC_DIV 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_AHB 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_APB 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_DMAC 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* peripheral device clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_GPIO 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_BISP 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLK_CSI0 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLK_CSI1 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLK_DE0 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_DE1 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLK_DE2 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLK_DE3 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLK_DSI 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_GPU 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLK_GPU_CORE 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_GPU_MEM 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLK_GPU_SYS 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLK_HDE 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLK_I2C0 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLK_I2C1 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLK_I2C2 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLK_I2C3 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLK_I2C4 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLK_I2C5 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLK_I2SRX 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CLK_I2STX 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CLK_IMX 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CLK_LCD 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CLK_NAND0 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLK_NAND1 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CLK_PWM0 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CLK_PWM1 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLK_PWM2 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CLK_PWM3 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLK_PWM4 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CLK_PWM5 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CLK_SD0 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CLK_SD1 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CLK_SD2 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CLK_SD3 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CLK_SENSOR 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CLK_SPEED_SENSOR 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CLK_SPI0 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CLK_SPI1 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CLK_SPI2 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CLK_SPI3 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CLK_THERMAL_SENSOR 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CLK_UART0 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CLK_UART1 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CLK_UART2 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CLK_UART3 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CLK_UART4 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CLK_UART5 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CLK_UART6 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CLK_VCE 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CLK_VDE 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CLK_USB3_480MPLL0 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CLK_USB3_480MPHY0 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CLK_USB3_5GPHY 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CLK_USB3_CCE 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CLK_USB3_MAC 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_TIMER 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_HDMI_AUDIO 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_24M 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_EDP 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_24M_EDP 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_EDP_PLL 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_EDP_LINK 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_USB2H0_PLLEN 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLK_USB2H0_PHY 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_USB2H0_CCE 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_USB2H1_PLLEN 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_USB2H1_PHY 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLK_USB2H1_CCE 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLK_DDR0 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_DDR1 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLK_DMM 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLK_ETH_MAC 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLK_RMII_REF 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLK_NR_CLKS (CLK_RMII_REF + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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