^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Device Tree binding constants for Actions Semi S700 Clock Management Unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 Actions Semi Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: David Liu <liuwei@actions-semi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Pathiban Nallathambi <pn@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Saravanan Sekar <sravanhome@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __DT_BINDINGS_CLOCK_S700_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __DT_BINDINGS_CLOCK_S700_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* pll clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_CORE_PLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_DEV_PLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_DDR_PLL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_NAND_PLL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_DISPLAY_PLL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_TVOUT_PLL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_CVBS_PLL 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_AUDIO_PLL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_ETHERNET_PLL 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* system clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_CPU 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_DEV 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_AHB 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_APB 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_DMAC 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_NOC0_CLK_MUX 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_NOC1_CLK_MUX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_HP_CLK_MUX 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_HP_CLK_DIV 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_NOC1_CLK_DIV 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_NOC0 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_NOC1 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLK_SENOR_SRC 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* peripheral device clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLK_GPIO 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_TIMER 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLK_DSI 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLK_CSI 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLK_SI 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLK_DE 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_HDE 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLK_VDE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_VCE 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLK_NAND 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLK_SD0 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLK_SD1 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLK_SD2 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLK_UART0 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLK_UART1 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLK_UART2 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLK_UART3 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLK_UART4 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CLK_UART5 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CLK_UART6 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CLK_PWM0 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLK_PWM1 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CLK_PWM2 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CLK_PWM3 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLK_PWM4 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CLK_PWM5 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLK_GPU3D 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CLK_I2C0 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CLK_I2C1 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CLK_I2C2 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CLK_I2C3 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CLK_SPI0 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CLK_SPI1 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CLK_SPI2 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CLK_SPI3 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CLK_USB3_480MPLL0 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CLK_USB3_480MPHY0 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CLK_USB3_5GPHY 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CLK_USB3_CCE 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CLK_USB3_MAC 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CLK_LCD 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CLK_HDMI_AUDIO 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CLK_I2SRX 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CLK_I2STX 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CLK_SENSOR0 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CLK_SENSOR1 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CLK_HDMI_DEV 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_ETHERNET 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_RMII_REF 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_USB2H0_PLLEN 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_USB2H0_PHY 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_USB2H0_CCE 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_USB2H1_PLLEN 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_USB2H1_PHY 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_USB2H1_CCE 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_TVOUT 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLK_THERMAL_SENSOR 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLK_IRC_SWITCH 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_PCM1 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_NR_CLKS (CLK_PCM1 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif /* __DT_BINDINGS_CLOCK_S700_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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