Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Device Tree binding constants for Actions Semi S500 Clock Management Unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2014 Actions Semi Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (c) 2018 LSI-TEC - Caninos Loucos
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef __DT_BINDINGS_CLOCK_S500_CMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __DT_BINDINGS_CLOCK_S500_CMU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CLK_NONE		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* fixed rate clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_LOSC		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_HOSC		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* pll clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_CORE_PLL		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_DEV_PLL		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_DDR_PLL		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_NAND_PLL		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_DISPLAY_PLL		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_ETHERNET_PLL	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_AUDIO_PLL		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* system clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_DEV			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_H			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_AHBPREDIV		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_AHB			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_DE			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_BISP		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_VCE			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_VDE			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* peripheral device clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_TIMER		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_I2C0		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_I2C1		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLK_I2C2		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLK_I2C3		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLK_PWM0		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLK_PWM1		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_PWM2		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLK_PWM3		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLK_PWM4		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLK_PWM5		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLK_SD0			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_SD1			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLK_SD2			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_SENSOR0		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLK_SENSOR1		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLK_SPI0		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLK_SPI1		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLK_SPI2		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLK_SPI3		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLK_UART0		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLK_UART1		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLK_UART2		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLK_UART3		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLK_UART4		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CLK_UART5		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CLK_UART6		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CLK_DE1			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CLK_DE2			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLK_I2SRX		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CLK_I2STX		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CLK_HDMI_AUDIO		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLK_HDMI		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CLK_SPDIF		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLK_NAND		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CLK_ECC			53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CLK_RMII_REF		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CLK_GPIO		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* system clock (part 2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CLK_APB			56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CLK_DMAC		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CLK_NR_CLKS		(CLK_DMAC + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #endif /* __DT_BINDINGS_CLOCK_S500_CMU_H */