^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /* This file defines field values used by the versaclock 6 family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for defining output type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define VC5_LVPECL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define VC5_CMOS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define VC5_HCSL33 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define VC5_LVDS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define VC5_CMOS2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define VC5_CMOSD 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define VC5_HCSL25 6