Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Device Tree defines for Lochnagar clocking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2017-2018 Cirrus Logic, Inc. and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *                         Cirrus Logic International Semiconductor Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Author: Charles Keepax <ckeepax@opensource.cirrus.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef DT_BINDINGS_CLK_LOCHNAGAR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DT_BINDINGS_CLK_LOCHNAGAR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define LOCHNAGAR_CDC_MCLK1		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define LOCHNAGAR_CDC_MCLK2		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define LOCHNAGAR_DSP_CLKIN		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define LOCHNAGAR_GF_CLKOUT1		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define LOCHNAGAR_GF_CLKOUT2		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LOCHNAGAR_PSIA1_MCLK		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LOCHNAGAR_PSIA2_MCLK		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LOCHNAGAR_SPDIF_MCLK		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LOCHNAGAR_ADAT_MCLK		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LOCHNAGAR_SOUNDCARD_MCLK	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LOCHNAGAR_SPDIF_CLKOUT		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #endif