^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2015 NVIDIA Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the rights to use, copy, modify, merge, publish, distribute, sub license,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The above copyright notice and this permission notice (including the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * next paragraph) shall be included in all copies or substantial portions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #ifndef DRM_SCDC_HELPER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DRM_SCDC_HELPER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SCDC_SINK_VERSION 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SCDC_SOURCE_VERSION 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SCDC_UPDATE_0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SCDC_READ_REQUEST_TEST (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SCDC_CED_UPDATE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SCDC_STATUS_UPDATE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SCDC_UPDATE_1 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SCDC_TMDS_CONFIG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SCDC_TMDS_BIT_CLOCK_RATIO_BY_10 (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SCDC_SCRAMBLING_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SCDC_SCRAMBLER_STATUS 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SCDC_SCRAMBLING_STATUS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SCDC_CONFIG_0 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SCDC_READ_REQUEST_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SCDC_STATUS_FLAGS_0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SCDC_CH2_LOCK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SCDC_CH1_LOCK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SCDC_CH0_LOCK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SCDC_CH_LOCK_MASK (SCDC_CH2_LOCK | SCDC_CH1_LOCK | SCDC_CH0_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SCDC_CLOCK_DETECT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SCDC_STATUS_FLAGS_1 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SCDC_ERR_DET_0_L 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SCDC_ERR_DET_0_H 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SCDC_ERR_DET_1_L 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SCDC_ERR_DET_1_H 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SCDC_ERR_DET_2_L 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SCDC_ERR_DET_2_H 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SCDC_CHANNEL_VALID (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SCDC_ERR_DET_CHECKSUM 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SCDC_TEST_CONFIG_0 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SCDC_TEST_READ_REQUEST (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SCDC_TEST_READ_REQUEST_DELAY(x) ((x) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SCDC_MANUFACTURER_IEEE_OUI 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SCDC_MANUFACTURER_IEEE_OUI_SIZE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SCDC_DEVICE_ID 0xd3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SCDC_DEVICE_ID_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SCDC_DEVICE_HARDWARE_REVISION 0xdb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SCDC_GET_DEVICE_HARDWARE_REVISION_MAJOR(x) (((x) >> 4) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SCDC_GET_DEVICE_HARDWARE_REVISION_MINOR(x) (((x) >> 0) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SCDC_DEVICE_SOFTWARE_MAJOR_REVISION 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SCDC_DEVICE_SOFTWARE_MINOR_REVISION 0xdd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SCDC_MANUFACTURER_SPECIFIC 0xde
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SCDC_MANUFACTURER_SPECIFIC_SIZE 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const void *buffer, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * drm_scdc_readb - read a single byte from SCDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @adapter: I2C adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @offset: offset of register to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @value: return location for the register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Reads a single byte from SCDC. This is a convenience wrapper around the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * drm_scdc_read() function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * 0 on success or a negative error code on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline int drm_scdc_readb(struct i2c_adapter *adapter, u8 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return drm_scdc_read(adapter, offset, value, sizeof(*value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * drm_scdc_writeb - write a single byte to SCDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @adapter: I2C adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @offset: offset of register to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @value: return location for the register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * Writes a single byte to SCDC. This is a convenience wrapper around the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * drm_scdc_write() function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * 0 on success or a negative error code on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static inline int drm_scdc_writeb(struct i2c_adapter *adapter, u8 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return drm_scdc_write(adapter, offset, &value, sizeof(value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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