^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright © 2006 Keith Packard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright © 2007-2008 Dave Airlie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright © 2007-2008 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Jesse Barnes <jesse.barnes@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright © 2014 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Daniel Vetter <daniel.vetter@ffwll.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #ifndef __DRM_MODES_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define __DRM_MODES_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/hdmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <drm/drm_mode_object.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <drm/drm_connector.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct videomode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Note on terminology: here, for brevity and convenience, we refer to connector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * control chips as 'CRTCs'. They can control any type of connector, VGA, LVDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * DVI, etc. And 'screen' refers to the whole of the visible display, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * may span multiple monitors (and therefore multiple CRTC and connector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * structures).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * enum drm_mode_status - hardware support status of a mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @MODE_OK: Mode OK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @MODE_HSYNC: hsync out of range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @MODE_VSYNC: vsync out of range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @MODE_H_ILLEGAL: mode has illegal horizontal timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @MODE_V_ILLEGAL: mode has illegal vertical timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @MODE_BAD_WIDTH: requires an unsupported linepitch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @MODE_NOMODE: no mode with a matching name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @MODE_NO_INTERLACE: interlaced mode not supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @MODE_NO_DBLESCAN: doublescan mode not supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @MODE_NO_VSCAN: multiscan mode not supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @MODE_MEM: insufficient video memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @MODE_VIRTUAL_X: mode width too large for specified virtual size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @MODE_VIRTUAL_Y: mode height too large for specified virtual size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @MODE_MEM_VIRT: insufficient video memory given virtual size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @MODE_NOCLOCK: no fixed clock available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @MODE_CLOCK_HIGH: clock required is too high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @MODE_CLOCK_LOW: clock required is too low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @MODE_CLOCK_RANGE: clock/mode isn't in a ClockRange
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @MODE_BAD_HVALUE: horizontal timing was out of range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @MODE_BAD_VVALUE: vertical timing was out of range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @MODE_BAD_VSCAN: VScan value out of range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @MODE_HSYNC_NARROW: horizontal sync too narrow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @MODE_HSYNC_WIDE: horizontal sync too wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @MODE_HBLANK_NARROW: horizontal blanking too narrow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @MODE_HBLANK_WIDE: horizontal blanking too wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @MODE_VSYNC_NARROW: vertical sync too narrow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @MODE_VSYNC_WIDE: vertical sync too wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @MODE_VBLANK_NARROW: vertical blanking too narrow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @MODE_VBLANK_WIDE: vertical blanking too wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @MODE_PANEL: exceeds panel dimensions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @MODE_INTERLACE_WIDTH: width too large for interlaced mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @MODE_ONE_WIDTH: only one width is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @MODE_ONE_HEIGHT: only one height is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @MODE_ONE_SIZE: only one resolution is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @MODE_NO_REDUCED: monitor doesn't accept reduced blanking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @MODE_NO_STEREO: stereo modes not supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @MODE_NO_420: ycbcr 420 modes not supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @MODE_STALE: mode has become stale
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @MODE_BAD: unspecified reason
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @MODE_ERROR: error condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * This enum is used to filter out modes not supported by the driver/hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * combination.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) enum drm_mode_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MODE_OK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MODE_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MODE_VSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MODE_H_ILLEGAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MODE_V_ILLEGAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MODE_BAD_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MODE_NOMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MODE_NO_INTERLACE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MODE_NO_DBLESCAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MODE_NO_VSCAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MODE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MODE_VIRTUAL_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MODE_VIRTUAL_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MODE_MEM_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MODE_NOCLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MODE_CLOCK_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MODE_CLOCK_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MODE_CLOCK_RANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MODE_BAD_HVALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MODE_BAD_VVALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MODE_BAD_VSCAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MODE_HSYNC_NARROW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MODE_HSYNC_WIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MODE_HBLANK_NARROW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MODE_HBLANK_WIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MODE_VSYNC_NARROW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MODE_VSYNC_WIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MODE_VBLANK_NARROW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MODE_VBLANK_WIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MODE_PANEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MODE_INTERLACE_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MODE_ONE_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MODE_ONE_HEIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MODE_ONE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MODE_NO_REDUCED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MODE_NO_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MODE_NO_420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MODE_STALE = -3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MODE_BAD = -2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MODE_ERROR = -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DRM_MODE(nm, t, c, hd, hss, hse, ht, hsk, vd, vss, vse, vt, vs, f) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .name = nm, .status = 0, .type = (t), .clock = (c), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .htotal = (ht), .hskew = (hsk), .vdisplay = (vd), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .vscan = (vs), .flags = (f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * DRM_SIMPLE_MODE - Simple display mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @hd: Horizontal resolution, width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @vd: Vertical resolution, height
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @hd_mm: Display width in millimeters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @vd_mm: Display height in millimeters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * This macro initializes a &drm_display_mode that only contains info about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * resolution and physical size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DRM_SIMPLE_MODE(hd, vd, hd_mm, vd_mm) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .type = DRM_MODE_TYPE_DRIVER, .clock = 1 /* pass validation */, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .hdisplay = (hd), .hsync_start = (hd), .hsync_end = (hd), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .htotal = (hd), .vdisplay = (vd), .vsync_start = (vd), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .vsync_end = (vd), .vtotal = (vd), .width_mm = (hd_mm), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .height_mm = (vd_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CRTC_INTERLACE_HALVE_V (1 << 0) /* halve V values for interlacing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CRTC_STEREO_DOUBLE (1 << 1) /* adjust timings for stereo modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CRTC_NO_DBLSCAN (1 << 2) /* don't adjust doublescan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CRTC_NO_VSCAN (1 << 3) /* don't adjust doublescan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CRTC_STEREO_DOUBLE_ONLY (CRTC_STEREO_DOUBLE | CRTC_NO_DBLSCAN | CRTC_NO_VSCAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DRM_MODE_FLAG_3D_MAX DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DRM_MODE_MATCH_TIMINGS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DRM_MODE_MATCH_CLOCK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DRM_MODE_MATCH_FLAGS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DRM_MODE_MATCH_3D_FLAGS (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DRM_MODE_MATCH_ASPECT_RATIO (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * struct drm_display_mode - DRM kernel-internal display mode structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @hdisplay: horizontal display size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @hsync_start: horizontal sync start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @hsync_end: horizontal sync end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @htotal: horizontal total size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @hskew: horizontal skew?!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @vdisplay: vertical display size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * @vsync_start: vertical sync start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @vsync_end: vertical sync end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @vtotal: vertical total size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @vscan: vertical scan?!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * @crtc_hdisplay: hardware mode horizontal display size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * @crtc_hblank_start: hardware mode horizontal blank start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * @crtc_hblank_end: hardware mode horizontal blank end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * @crtc_hsync_start: hardware mode horizontal sync start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * @crtc_hsync_end: hardware mode horizontal sync end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * @crtc_htotal: hardware mode horizontal total size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * @crtc_hskew: hardware mode horizontal skew?!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @crtc_vdisplay: hardware mode vertical display size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @crtc_vblank_start: hardware mode vertical blank start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @crtc_vblank_end: hardware mode vertical blank end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @crtc_vsync_start: hardware mode vertical sync start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @crtc_vsync_end: hardware mode vertical sync end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * @crtc_vtotal: hardware mode vertical total size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * The horizontal and vertical timings are defined per the following diagram.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * Active Front Sync Back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * Region Porch Porch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * <-----------------------><----------------><-------------><-------------->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * //////////////////////|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * ////////////////////// |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * ////////////////////// |.................. ................
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * _______________
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * <----- [hv]display ----->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * <------------- [hv]sync_start ------------>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * <--------------------- [hv]sync_end --------------------->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * <-------------------------------- [hv]total ----------------------------->*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * This structure contains two copies of timings. First are the plain timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * which specify the logical mode, as it would be for a progressive 1:1 scanout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * at the refresh rate userspace can observe through vblank timestamps. Then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * there's the hardware timings, which are corrected for interlacing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * double-clocking and similar things. They are provided as a convenience, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * can be appropriately computed using drm_mode_set_crtcinfo().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * For printing you can use %DRM_MODE_FMT and DRM_MODE_ARG().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct drm_display_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * @clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * Pixel clock in kHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int clock; /* in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u16 hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u16 hsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u16 hsync_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u16 htotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u16 hskew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u16 vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u16 vsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u16 vsync_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u16 vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u16 vscan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * @flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * Sync and timing flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * - DRM_MODE_FLAG_PHSYNC: horizontal sync is active high.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * - DRM_MODE_FLAG_NHSYNC: horizontal sync is active low.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * - DRM_MODE_FLAG_PVSYNC: vertical sync is active high.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * - DRM_MODE_FLAG_NVSYNC: vertical sync is active low.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * - DRM_MODE_FLAG_INTERLACE: mode is interlaced.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * - DRM_MODE_FLAG_DBLSCAN: mode uses doublescan.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * - DRM_MODE_FLAG_CSYNC: mode uses composite sync.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * - DRM_MODE_FLAG_PCSYNC: composite sync is active high.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * - DRM_MODE_FLAG_NCSYNC: composite sync is active low.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * - DRM_MODE_FLAG_HSKEW: hskew provided (not used?).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * - DRM_MODE_FLAG_BCAST: <deprecated>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * - DRM_MODE_FLAG_PIXMUX: <deprecated>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * - DRM_MODE_FLAG_DBLCLK: double-clocked mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * - DRM_MODE_FLAG_CLKDIV2: half-clocked mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * Additionally there's flags to specify how 3D modes are packed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * - DRM_MODE_FLAG_3D_NONE: normal, non-3D mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * - DRM_MODE_FLAG_3D_FRAME_PACKING: 2 full frames for left and right.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * - DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: interleaved like fields.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * - DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: interleaved lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * - DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: side-by-side full frames.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * - DRM_MODE_FLAG_3D_L_DEPTH: ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * - DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * - DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: frame split into top and bottom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * parts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * - DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: frame split into left and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * right parts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * @crtc_clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * Actual pixel or dot clock in the hardware. This differs from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * logical @clock when e.g. using interlacing, double-clocking, stereo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * modes or other fancy stuff that changes the timings and signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * actually sent over the wire.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * This is again in kHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * Note that with digital outputs like HDMI or DP there's usually a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * massive confusion between the dot clock and the signal clock at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * bit encoding level. Especially when a 8b/10b encoding is used and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * difference is exactly a factor of 10.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int crtc_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u16 crtc_hdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u16 crtc_hblank_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u16 crtc_hblank_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u16 crtc_hsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u16 crtc_hsync_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u16 crtc_htotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u16 crtc_hskew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u16 crtc_vdisplay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u16 crtc_vblank_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u16 crtc_vblank_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u16 crtc_vsync_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u16 crtc_vsync_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u16 crtc_vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * @width_mm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * Addressable size of the output in mm, projectors should set this to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u16 width_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * @height_mm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * Addressable size of the output in mm, projectors should set this to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u16 height_mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * @type:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * A bitmask of flags, mostly about the source of a mode. Possible flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * - DRM_MODE_TYPE_PREFERRED: Preferred mode, usually the native
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * resolution of an LCD panel. There should only be one preferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * mode per connector at any given time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * - DRM_MODE_TYPE_DRIVER: Mode created by the driver, which is all of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * them really. Drivers must set this bit for all modes they create
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * and expose to userspace.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * - DRM_MODE_TYPE_USERDEF: Mode defined or selected via the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * command line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * Plus a big list of flags which shouldn't be used at all, but are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * still around since these flags are also used in the userspace ABI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * We no longer accept modes with these types though:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * - DRM_MODE_TYPE_BUILTIN: Meant for hard-coded modes, unused.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * Use DRM_MODE_TYPE_DRIVER instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * - DRM_MODE_TYPE_DEFAULT: Again a leftover, use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * DRM_MODE_TYPE_PREFERRED instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * - DRM_MODE_TYPE_CLOCK_C and DRM_MODE_TYPE_CRTC_C: Define leftovers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * which are stuck around for hysterical raisins only. No one has an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * idea what they were meant for. Don't use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * @expose_to_userspace:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * Indicates whether the mode is to be exposed to the userspace.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * This is to maintain a set of exposed modes while preparing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * user-mode's list in drm_mode_getconnector ioctl. The purpose of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * this only lies in the ioctl function, and is not to be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * outside the function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) bool expose_to_userspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * @head:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * struct list_head for mode lists.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct list_head head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * @name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * Human-readable name of the mode, filled out with drm_mode_set_name().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) char name[DRM_DISPLAY_MODE_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * @status:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * Status of the mode, used to filter out modes not supported by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * hardware. See enum &drm_mode_status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) enum drm_mode_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * @picture_aspect_ratio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * Field for setting the HDMI picture aspect ratio of a mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) enum hdmi_picture_aspect picture_aspect_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * DRM_MODE_FMT - printf string for &struct drm_display_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define DRM_MODE_FMT "\"%s\": %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * DRM_MODE_ARG - printf arguments for &struct drm_display_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * @m: display mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define DRM_MODE_ARG(m) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) (m)->name, drm_mode_vrefresh(m), (m)->clock, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) (m)->hdisplay, (m)->hsync_start, (m)->hsync_end, (m)->htotal, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) (m)->vdisplay, (m)->vsync_start, (m)->vsync_end, (m)->vtotal, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) (m)->type, (m)->flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define obj_to_mode(x) container_of(x, struct drm_display_mode, base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * drm_mode_is_stereo - check for stereo mode flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * @mode: drm_display_mode to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * True if the mode is one of the stereo modes (like side-by-side), false if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static inline bool drm_mode_is_stereo(const struct drm_display_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return mode->flags & DRM_MODE_FLAG_3D_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct drm_connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct drm_cmdline_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct drm_display_mode *drm_mode_create(struct drm_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) void drm_mode_destroy(struct drm_device *dev, struct drm_display_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) void drm_mode_convert_to_umode(struct drm_mode_modeinfo *out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) const struct drm_display_mode *in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) int drm_mode_convert_umode(struct drm_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct drm_display_mode *out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) const struct drm_mode_modeinfo *in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) void drm_mode_probed_add(struct drm_connector *connector, struct drm_display_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) void drm_mode_debug_printmodeline(const struct drm_display_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) bool drm_mode_is_420_only(const struct drm_display_info *display,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) const struct drm_display_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) bool drm_mode_is_420_also(const struct drm_display_info *display,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) const struct drm_display_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) bool drm_mode_is_420(const struct drm_display_info *display,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) const struct drm_display_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct drm_display_mode *drm_cvt_mode(struct drm_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int hdisplay, int vdisplay, int vrefresh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) bool reduced, bool interlaced,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) bool margins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct drm_display_mode *drm_gtf_mode(struct drm_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int hdisplay, int vdisplay, int vrefresh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) bool interlaced, int margins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct drm_display_mode *drm_gtf_mode_complex(struct drm_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int hdisplay, int vdisplay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) int vrefresh, bool interlaced,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int margins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int GTF_M, int GTF_2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int GTF_K, int GTF_2J);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) void drm_display_mode_from_videomode(const struct videomode *vm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct drm_display_mode *dmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) void drm_display_mode_to_videomode(const struct drm_display_mode *dmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct videomode *vm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) void drm_bus_flags_from_videomode(const struct videomode *vm, u32 *bus_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int of_get_drm_display_mode(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct drm_display_mode *dmode, u32 *bus_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) void drm_mode_set_name(struct drm_display_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int drm_mode_vrefresh(const struct drm_display_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) void drm_mode_get_hv_timing(const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int *hdisplay, int *vdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) void drm_mode_set_crtcinfo(struct drm_display_mode *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int adjust_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) void drm_mode_copy(struct drm_display_mode *dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) const struct drm_display_mode *src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct drm_display_mode *drm_mode_duplicate(struct drm_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) const struct drm_display_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) bool drm_mode_match(const struct drm_display_mode *mode1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) const struct drm_display_mode *mode2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) unsigned int match_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) bool drm_mode_equal(const struct drm_display_mode *mode1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) const struct drm_display_mode *mode2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) const struct drm_display_mode *mode2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) const struct drm_display_mode *mode2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* for use by the crtc helper probe functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) enum drm_mode_status drm_mode_validate_driver(struct drm_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) const struct drm_display_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) enum drm_mode_status drm_mode_validate_size(const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int maxX, int maxY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) enum drm_mode_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) drm_mode_validate_ycbcr420(const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct drm_connector *connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) void drm_mode_prune_invalid(struct drm_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct list_head *mode_list, bool verbose);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) void drm_mode_sort(struct list_head *mode_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) void drm_connector_list_update(struct drm_connector *connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* parsing cmdline modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) drm_mode_parse_command_line_for_connector(const char *mode_option,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) const struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct drm_cmdline_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct drm_display_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) drm_mode_create_from_cmdline_mode(struct drm_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct drm_cmdline_mode *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #endif /* __DRM_MODES_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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