^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MIPI Display Bus Interface (DBI) LCD controller support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2016 Noralf Trønnes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __LINUX_MIPI_DBI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __LINUX_MIPI_DBI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <drm/drm_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <drm/drm_simple_kms_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct drm_rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct spi_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct gpio_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * struct mipi_dbi - MIPI DBI interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct mipi_dbi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * @cmdlock: Command lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct mutex cmdlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @command: Bus specific callback executing commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int (*command)(struct mipi_dbi *dbi, u8 *cmd, u8 *param, size_t num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @read_commands: Array of read commands terminated by a zero entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Reading is disabled if this is NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) const u8 *read_commands;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @swap_bytes: Swap bytes in buffer before transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) bool swap_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @reset: Optional reset gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct gpio_desc *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Type C specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @spi: SPI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @dc: Optional D/C gpio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct gpio_desc *dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @tx_buf9: Buffer used for Option 1 9-bit conversion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void *tx_buf9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @tx_buf9_len: Size of tx_buf9.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) size_t tx_buf9_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * struct mipi_dbi_dev - MIPI DBI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct mipi_dbi_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @drm: DRM device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct drm_device drm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @pipe: Display pipe structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct drm_simple_display_pipe pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @connector: Connector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct drm_connector connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @mode: Fixed display mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct drm_display_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @tx_buf: Buffer used for transfer (copy clip rect area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u16 *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @rotation: initial rotation in degrees Counter Clock Wise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int rotation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @left_offset: Horizontal offset of the display relative to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * controller's driver array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int left_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @top_offset: Vertical offset of the display relative to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * controller's driver array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int top_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @backlight: backlight device (optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct backlight_device *backlight;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @regulator: power regulator (optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct regulator *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @dbi: MIPI DBI interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct mipi_dbi dbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static inline struct mipi_dbi_dev *drm_to_mipi_dbi_dev(struct drm_device *drm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return container_of(drm, struct mipi_dbi_dev, drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct gpio_desc *dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) const struct drm_simple_display_pipe_funcs *funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) const uint32_t *formats, unsigned int format_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int rotation, size_t tx_buf_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int mipi_dbi_dev_init(struct mipi_dbi_dev *dbidev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) const struct drm_simple_display_pipe_funcs *funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) const struct drm_display_mode *mode, unsigned int rotation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct drm_plane_state *old_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) void mipi_dbi_enable_flush(struct mipi_dbi_dev *dbidev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct drm_crtc_state *crtc_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct drm_plane_state *plan_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) void mipi_dbi_hw_reset(struct mipi_dbi *dbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) bool mipi_dbi_display_is_on(struct mipi_dbi *dbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int mipi_dbi_poweron_reset(struct mipi_dbi_dev *dbidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev *dbidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u8 bpw, const void *buf, size_t len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, const u8 *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) size_t len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct drm_rect *clip, bool swap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * mipi_dbi_command - MIPI DCS command with optional parameter(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @dbi: MIPI DBI structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @cmd: Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @seq...: Optional parameter(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * Send MIPI DCS command to the controller. Use mipi_dbi_command_read() for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * get/read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * Returns:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * Zero on success, negative error code on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define mipi_dbi_command(dbi, cmd, seq...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) const u8 d[] = { seq }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) mipi_dbi_command_stackbuf(dbi, cmd, d, ARRAY_SIZE(d)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) void mipi_dbi_debugfs_init(struct drm_minor *minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define mipi_dbi_debugfs_init NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #endif /* __LINUX_MIPI_DBI_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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