^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: MIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2017 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Sean Paul <seanpaul@chromium.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _DRM_HDCP_H_INCLUDED_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _DRM_HDCP_H_INCLUDED_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Period of hdcp checks (to ensure we're still authenticated) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DRM_HDCP_CHECK_PERIOD_MS (128 * 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DRM_HDCP2_CHECK_PERIOD_MS 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Shared lengths/masks between HDMI/DVI/DisplayPort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DRM_HDCP_AN_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DRM_HDCP_BSTATUS_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DRM_HDCP_KSV_LEN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DRM_HDCP_RI_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DRM_HDCP_V_PRIME_PART_LEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DRM_HDCP_V_PRIME_NUM_PARTS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Slave address for the HDCP registers in the receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRM_HDCP_DDC_ADDR 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Value to use at the end of the SHA-1 bytestream used for repeaters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DRM_HDCP_SHA1_TERMINATOR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* HDCP register offsets for HDMI/DVI devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRM_HDCP_DDC_BKSV 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DRM_HDCP_DDC_RI_PRIME 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRM_HDCP_DDC_AKSV 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DRM_HDCP_DDC_AN 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DRM_HDCP_DDC_V_PRIME(h) (0x20 + h * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DRM_HDCP_DDC_BCAPS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DRM_HDCP_DDC_BSTATUS 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DRM_HDCP_DDC_KSV_FIFO 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DRM_HDCP_1_4_SRM_ID 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DRM_HDCP_1_4_VRL_LENGTH_SIZE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DRM_HDCP_1_4_DCP_SIG_SIZE 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Protocol message definition for HDCP2.2 specification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Protected content streams are classified into 2 types:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * - Type0: Can be transmitted with HDCP 1.4+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * - Type1: Can be transmitted with HDCP 2.2+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HDCP_STREAM_TYPE0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HDCP_STREAM_TYPE1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* HDCP2.2 Msg IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HDCP_2_2_NULL_MSG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HDCP_2_2_AKE_INIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HDCP_2_2_AKE_SEND_CERT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HDCP_2_2_AKE_NO_STORED_KM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HDCP_2_2_AKE_STORED_KM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HDCP_2_2_AKE_SEND_HPRIME 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define HDCP_2_2_AKE_SEND_PAIRING_INFO 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define HDCP_2_2_LC_INIT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define HDCP_2_2_LC_SEND_LPRIME 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HDCP_2_2_SKE_SEND_EKS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define HDCP_2_2_REP_SEND_RECVID_LIST 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define HDCP_2_2_REP_SEND_ACK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define HDCP_2_2_REP_STREAM_MANAGE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define HDCP_2_2_REP_STREAM_READY 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define HDCP_2_2_RTX_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define HDCP_2_2_RRX_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HDCP_2_2_K_PUB_RX_MOD_N_LEN 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define HDCP_2_2_K_PUB_RX_EXP_E_LEN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HDCP_2_2_K_PUB_RX_LEN (HDCP_2_2_K_PUB_RX_MOD_N_LEN + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) HDCP_2_2_K_PUB_RX_EXP_E_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define HDCP_2_2_DCP_LLC_SIG_LEN 384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define HDCP_2_2_E_KPUB_KM_LEN 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define HDCP_2_2_E_KH_KM_M_LEN (16 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HDCP_2_2_H_PRIME_LEN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define HDCP_2_2_E_KH_KM_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HDCP_2_2_RN_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HDCP_2_2_L_PRIME_LEN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define HDCP_2_2_E_DKEY_KS_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define HDCP_2_2_RIV_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HDCP_2_2_SEQ_NUM_LEN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HDCP_2_2_V_PRIME_HALF_LEN (HDCP_2_2_L_PRIME_LEN / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HDCP_2_2_RECEIVER_ID_LEN DRM_HDCP_KSV_LEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HDCP_2_2_MAX_DEVICE_COUNT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define HDCP_2_2_RECEIVER_IDS_MAX_LEN (HDCP_2_2_RECEIVER_ID_LEN * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) HDCP_2_2_MAX_DEVICE_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HDCP_2_2_MPRIME_LEN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Following Macros take a byte at a time for bit(s) masking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * TODO: This has to be changed for DP MST, as multiple stream on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * same port is possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * For HDCP2.2 on HDMI and DP SST this value is always 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HDCP_2_2_TXCAP_MASK_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HDCP_2_2_RXCAPS_LEN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HDCP_2_2_DP_HDCP_CAPABLE(x) ((x) & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define HDCP_2_2_RXINFO_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* HDCP1.x compliant device in downstream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HDCP_2_2_HDCP1_DEVICE_CONNECTED(x) ((x) & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* HDCP2.0 Compliant repeater in downstream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HDCP_2_2_HDCP_2_0_REP_CONNECTED(x) ((x) & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HDCP_2_2_MAX_CASCADE_EXCEEDED(x) ((x) & BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HDCP_2_2_MAX_DEVS_EXCEEDED(x) ((x) & BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HDCP_2_2_DEV_COUNT_LO(x) (((x) & (0xF << 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define HDCP_2_2_DEV_COUNT_HI(x) ((x) & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HDCP_2_2_DEPTH(x) (((x) & (0x7 << 1)) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct hdcp2_cert_rx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u8 receiver_id[HDCP_2_2_RECEIVER_ID_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 kpub_rx[HDCP_2_2_K_PUB_RX_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u8 reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u8 dcp_signature[HDCP_2_2_DCP_LLC_SIG_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct hdcp2_streamid_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u8 stream_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u8 stream_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * The TxCaps field specified in the HDCP HDMI, DP specs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * This field is big endian as specified in the errata.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct hdcp2_tx_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Transmitter must set this to 0x2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u8 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Reserved for HDCP and DP Spec. Read as Zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 tx_cap_mask[HDCP_2_2_TXCAP_MASK_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Main structures for HDCP2.2 protocol communication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct hdcp2_ake_init {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u8 msg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u8 r_tx[HDCP_2_2_RTX_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct hdcp2_tx_caps tx_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct hdcp2_ake_send_cert {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u8 msg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct hdcp2_cert_rx cert_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u8 r_rx[HDCP_2_2_RRX_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u8 rx_caps[HDCP_2_2_RXCAPS_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct hdcp2_ake_no_stored_km {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u8 msg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 e_kpub_km[HDCP_2_2_E_KPUB_KM_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct hdcp2_ake_stored_km {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u8 msg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u8 e_kh_km_m[HDCP_2_2_E_KH_KM_M_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct hdcp2_ake_send_hprime {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u8 msg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u8 h_prime[HDCP_2_2_H_PRIME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct hdcp2_ake_send_pairing_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u8 msg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u8 e_kh_km[HDCP_2_2_E_KH_KM_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct hdcp2_lc_init {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u8 msg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u8 r_n[HDCP_2_2_RN_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct hdcp2_lc_send_lprime {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u8 msg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u8 l_prime[HDCP_2_2_L_PRIME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct hdcp2_ske_send_eks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u8 msg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u8 e_dkey_ks[HDCP_2_2_E_DKEY_KS_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u8 riv[HDCP_2_2_RIV_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct hdcp2_rep_send_receiverid_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u8 msg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u8 rx_info[HDCP_2_2_RXINFO_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u8 seq_num_v[HDCP_2_2_SEQ_NUM_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u8 v_prime[HDCP_2_2_V_PRIME_HALF_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 receiver_ids[HDCP_2_2_RECEIVER_IDS_MAX_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct hdcp2_rep_send_ack {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 msg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u8 v[HDCP_2_2_V_PRIME_HALF_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct hdcp2_rep_stream_manage {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u8 msg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u8 seq_num_m[HDCP_2_2_SEQ_NUM_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) __be16 k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct hdcp2_streamid_type streams[HDCP_2_2_MAX_CONTENT_STREAMS_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct hdcp2_rep_stream_ready {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u8 msg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u8 m_prime[HDCP_2_2_MPRIME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* HDCP2.2 TIMEOUTs in mSec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define HDCP_2_2_CERT_TIMEOUT_MS 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define HDCP_2_2_PAIRING_TIMEOUT_MS 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define HDCP_2_2_DP_LPRIME_TIMEOUT_MS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define HDCP_2_2_RECVID_LIST_TIMEOUT_MS 3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define HDCP_2_2_STREAM_READY_TIMEOUT_MS 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* HDMI HDCP2.2 Register Offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define HDCP_2_2_HDMI_REG_VER_OFFSET 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define HDCP_2_2_HDMI_REG_RD_MSG_OFFSET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define HDCP_2_2_HDMI_REG_DBG_OFFSET 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define HDCP_2_2_HDMI_SUPPORT_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define HDCP_2_2_RX_CAPS_VERSION_VAL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define HDCP_2_2_SEQ_NUM_MAX 0xFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Below macros take a byte at a time and mask the bit(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define HDCP_2_2_HDMI_RXSTATUS_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x) ((x) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * Helper functions to convert 24bit big endian hdcp sequence number to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * host format and back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u32 drm_hdcp_be24_to_cpu(const u8 seq_num[HDCP_2_2_SEQ_NUM_LEN])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return (u32)(seq_num[2] | seq_num[1] << 8 | seq_num[0] << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) void drm_hdcp_cpu_to_be24(u8 seq_num[HDCP_2_2_SEQ_NUM_LEN], u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) seq_num[0] = val >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) seq_num[1] = val >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) seq_num[2] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define DRM_HDCP_SRM_GEN1_MAX_BYTES (5 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define DRM_HDCP_1_4_SRM_ID 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define DRM_HDCP_SRM_ID_MASK (0xF << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define DRM_HDCP_1_4_VRL_LENGTH_SIZE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define DRM_HDCP_1_4_DCP_SIG_SIZE 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define DRM_HDCP_2_SRM_ID 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define DRM_HDCP_2_INDICATOR 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define DRM_HDCP_2_INDICATOR_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define DRM_HDCP_2_VRL_LENGTH_SIZE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define DRM_HDCP_2_DCP_SIG_SIZE 384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define DRM_HDCP_2_NO_OF_DEV_PLUS_RESERVED_SZ 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define DRM_HDCP_2_KSV_COUNT_2_LSBITS(byte) (((byte) & 0xC0) >> 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct hdcp_srm_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u8 srm_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) __be16 srm_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u8 srm_gen_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct drm_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct drm_connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int drm_hdcp_check_ksvs_revoked(struct drm_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u8 *ksvs, u32 ksv_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int drm_connector_attach_content_protection_property(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct drm_connector *connector, bool hdcp_content_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) void drm_hdcp_update_content_protection(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u64 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Content Type classification for HDCP2.2 vs others */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DRM_MODE_HDCP_CONTENT_TYPE0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define DRM_MODE_HDCP_CONTENT_TYPE1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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