^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright © 2007-2008 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Jesse Barnes <jesse.barnes@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #ifndef __DRM_EDID_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define __DRM_EDID_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/hdmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <drm/drm_mode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct drm_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct i2c_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EDID_LENGTH 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DDC_ADDR 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CEA_EXT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VTB_EXT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DI_EXT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LS_EXT 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MI_EXT 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DISPLAYID_EXT 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct est_timings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u8 t1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u8 t2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 mfg_rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EDID_TIMING_ASPECT_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* need to add 60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define EDID_TIMING_VFREQ_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct std_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u8 hsize; /* need to multiply by 8 then add 248 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u8 vfreq_aspect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DRM_EDID_PT_STEREO (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DRM_EDID_PT_INTERLACED (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* If detailed data is pixel timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct detailed_pixel_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 hactive_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 hblank_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 hactive_hblank_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u8 vactive_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u8 vblank_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 vactive_vblank_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u8 hsync_offset_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 hsync_pulse_width_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 vsync_offset_pulse_width_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 hsync_vsync_offset_pulse_width_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u8 width_mm_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 height_mm_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u8 width_height_mm_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 hborder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 vborder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* If it's not pixel timing, it'll be one of the below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct detailed_data_string {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 str[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DRM_EDID_RANGE_LIMITS_ONLY_FLAG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DRM_EDID_CVT_SUPPORT_FLAG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct detailed_data_monitor_range {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 min_vfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 max_vfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u8 min_hfreq_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u8 max_hfreq_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u8 pixel_clock_mhz; /* need to multiply by 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 hfreq_start_khz; /* need to multiply by 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 c; /* need to divide by 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) __le16 m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 j; /* need to divide by 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) } __attribute__((packed)) gtf2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u8 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u8 data1; /* high 6 bits: extra clock resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u8 data2; /* plus low 2 of above: max hactive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u8 supported_aspects;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u8 flags; /* preferred aspect and blanking support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u8 supported_scalings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u8 preferred_refresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) } __attribute__((packed)) cvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) } formula;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct detailed_data_wpindex {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 white_yx_lo; /* Lower 2 bits each */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u8 white_x_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u8 white_y_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u8 gamma; /* need to divide by 100 then add 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct detailed_data_color_point {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u8 windex1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u8 wpindex1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u8 windex2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u8 wpindex2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct cvt_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u8 code[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct detailed_non_pixel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8 pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) fb=color point data, fa=standard timing data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) f9=undefined, f8=mfg. reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u8 pad2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct detailed_data_string str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct detailed_data_monitor_range range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct detailed_data_wpindex color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct std_timing timings[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct cvt_timing cvt[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) } data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define EDID_DETAIL_EST_TIMINGS 0xf7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define EDID_DETAIL_CVT_3BYTE 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define EDID_DETAIL_STD_MODES 0xfa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define EDID_DETAIL_MONITOR_CPDATA 0xfb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define EDID_DETAIL_MONITOR_NAME 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define EDID_DETAIL_MONITOR_RANGE 0xfd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define EDID_DETAIL_MONITOR_STRING 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define EDID_DETAIL_MONITOR_SERIAL 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct detailed_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) __le16 pixel_clock; /* need to multiply by 10 KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct detailed_pixel_timing pixel_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct detailed_non_pixel other_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) } data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define DRM_EDID_INPUT_DIGITAL (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DRM_EDID_DIGITAL_TYPE_MASK (7 << 0) /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DRM_EDID_DIGITAL_TYPE_UNDEF (0 << 0) /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DRM_EDID_DIGITAL_TYPE_DVI (1 << 0) /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2 << 0) /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3 << 0) /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define DRM_EDID_DIGITAL_TYPE_MDDI (4 << 0) /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define DRM_EDID_DIGITAL_TYPE_DP (5 << 0) /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define DRM_EDID_DIGITAL_DFP_1_X (1 << 0) /* 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* If analog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* If digital */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define DRM_EDID_FEATURE_COLOR_MASK (3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define DRM_EDID_FEATURE_RGB (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define DRM_EDID_FEATURE_PM_STANDBY (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define DRM_EDID_HDMI_DC_48 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define DRM_EDID_HDMI_DC_36 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DRM_EDID_HDMI_DC_30 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define DRM_EDID_HDMI_DC_Y444 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* YCBCR 420 deep color modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define DRM_EDID_YCBCR420_DC_48 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define DRM_EDID_YCBCR420_DC_36 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define DRM_EDID_YCBCR420_DC_30 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) DRM_EDID_YCBCR420_DC_36 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) DRM_EDID_YCBCR420_DC_30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #ifdef CONFIG_NO_GKI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* HDMI 2.1 additional fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define DRM_EDID_MAX_FRL_RATE_MASK 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define DRM_EDID_FAPA_START_LOCATION (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define DRM_EDID_ALLM (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define DRM_EDID_FVA (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Deep Color specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define DRM_EDID_DC_30BIT_420 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define DRM_EDID_DC_36BIT_420 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define DRM_EDID_DC_48BIT_420 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* VRR specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define DRM_EDID_CNMVRR (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define DRM_EDID_CINEMA_VRR (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define DRM_EDID_MDELTA (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define DRM_EDID_VRR_MAX_UPPER_MASK 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define DRM_EDID_VRR_MAX_LOWER_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define DRM_EDID_VRR_MIN_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* DSC specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define DRM_EDID_DSC_10BPC (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define DRM_EDID_DSC_12BPC (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define DRM_EDID_DSC_16BPC (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define DRM_EDID_DSC_ALL_BPP (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define DRM_EDID_DSC_NATIVE_420 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define DRM_EDID_DSC_1P2 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define DRM_EDID_DSC_MAX_FRL_RATE_MASK 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define DRM_EDID_DSC_MAX_SLICES 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* ELD Header Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define DRM_ELD_HEADER_BLOCK_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define DRM_ELD_VER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) # define DRM_ELD_VER_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) # define DRM_ELD_VER_MASK (0x1f << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) # define DRM_ELD_VER_CEA861D (2 << 3) /* supports 861D or below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) # define DRM_ELD_VER_CANNED (0x1f << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define DRM_ELD_BASELINE_ELD_LEN 2 /* in dwords! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* ELD Baseline Block for ELD_Ver == 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define DRM_ELD_CEA_EDID_VER_MNL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) # define DRM_ELD_CEA_EDID_VER_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) # define DRM_ELD_CEA_EDID_VER_MASK (7 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) # define DRM_ELD_CEA_EDID_VER_NONE (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) # define DRM_ELD_CEA_EDID_VER_CEA861 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) # define DRM_ELD_CEA_EDID_VER_CEA861A (2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) # define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) # define DRM_ELD_MNL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) # define DRM_ELD_MNL_MASK (0x1f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define DRM_ELD_SAD_COUNT_CONN_TYPE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) # define DRM_ELD_SAD_COUNT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) # define DRM_ELD_SAD_COUNT_MASK (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) # define DRM_ELD_CONN_TYPE_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) # define DRM_ELD_CONN_TYPE_MASK (3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) # define DRM_ELD_CONN_TYPE_HDMI (0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) # define DRM_ELD_CONN_TYPE_DP (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) # define DRM_ELD_SUPPORTS_AI (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) # define DRM_ELD_SUPPORTS_HDCP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define DRM_ELD_AUD_SYNCH_DELAY 6 /* in units of 2 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) # define DRM_ELD_AUD_SYNCH_DELAY_MAX 0xfa /* 500 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define DRM_ELD_SPEAKER 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) # define DRM_ELD_SPEAKER_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) # define DRM_ELD_SPEAKER_RLRC (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) # define DRM_ELD_SPEAKER_FLRC (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) # define DRM_ELD_SPEAKER_RC (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) # define DRM_ELD_SPEAKER_RLR (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) # define DRM_ELD_SPEAKER_FC (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) # define DRM_ELD_SPEAKER_LFE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) # define DRM_ELD_SPEAKER_FLR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define DRM_ELD_PORT_ID 8 /* offsets 8..15 inclusive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) # define DRM_ELD_PORT_ID_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define DRM_ELD_MANUFACTURER_NAME0 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define DRM_ELD_MANUFACTURER_NAME1 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define DRM_ELD_PRODUCT_CODE0 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define DRM_ELD_PRODUCT_CODE1 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define DRM_ELD_MONITOR_NAME_STRING 20 /* offsets 20..(20+mnl-1) inclusive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define DRM_ELD_CEA_SAD(mnl, sad) (20 + (mnl) + 3 * (sad))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct edid {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u8 header[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Vendor & product info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u8 mfg_id[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u8 prod_code[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 serial; /* FIXME: byte order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u8 mfg_week;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u8 mfg_year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* EDID version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u8 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u8 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* Display info: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u8 input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u8 width_cm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u8 height_cm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u8 gamma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u8 features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Color characteristics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u8 red_green_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u8 black_white_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u8 red_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u8 red_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u8 green_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u8 green_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u8 blue_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u8 blue_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u8 white_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u8 white_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Est. timings and mfg rsvd timings*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct est_timings established_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* Standard timings 1-8*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct std_timing standard_timings[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Detailing timings 1-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct detailed_timing detailed_timings[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Number of 128 byte ext. blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u8 extensions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u8 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* Short Audio Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct cea_sad {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u8 format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u8 channels; /* max number of channels - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u8 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u8 byte2; /* meaning depends on format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct drm_encoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct drm_connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct drm_connector_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct drm_display_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int drm_av_sync_delay(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) const struct drm_display_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct edid *drm_load_edid_firmware(struct drm_connector *connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int __drm_set_edid_firmware_path(const char *path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int __drm_get_edid_firmware_path(char *buf, size_t bufsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static inline struct edid *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) drm_load_edid_firmware(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) const struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) const struct drm_display_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) const struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) const struct drm_display_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) const struct drm_connector_state *conn_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) const struct drm_connector_state *conn_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) const struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) const struct drm_display_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) enum hdmi_quantization_range rgb_quant_range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) const struct drm_connector_state *conn_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * drm_eld_mnl - Get ELD monitor name length in bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * @eld: pointer to an eld memory structure with mnl set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static inline int drm_eld_mnl(const uint8_t *eld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * drm_eld_sad - Get ELD SAD structures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * @eld: pointer to an eld memory structure with sad_count set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static inline const uint8_t *drm_eld_sad(const uint8_t *eld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned int ver, mnl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (ver != 2 && ver != 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) mnl = drm_eld_mnl(eld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (mnl > 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return eld + DRM_ELD_CEA_SAD(mnl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * drm_eld_sad_count - Get ELD SAD count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * @eld: pointer to an eld memory structure with sad_count set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static inline int drm_eld_sad_count(const uint8_t *eld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) DRM_ELD_SAD_COUNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * @eld: pointer to an eld memory structure with mnl and sad_count set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * This is a helper for determining the payload size of the baseline block, in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * drm_eld_size - Get ELD size in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * @eld: pointer to a complete eld memory structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * The returned value does not include the vendor block. It's vendor specific,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * and comprises of the remaining bytes in the ELD memory buffer after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * drm_eld_size() bytes of header and baseline block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * The returned value is guaranteed to be a multiple of 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static inline int drm_eld_size(const uint8_t *eld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * drm_eld_get_spk_alloc - Get speaker allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * @eld: pointer to an ELD memory structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * The returned value is the speakers mask. User has to use %DRM_ELD_SPEAKER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * field definitions to identify speakers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static inline u8 drm_eld_get_spk_alloc(const uint8_t *eld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return eld[DRM_ELD_SPEAKER] & DRM_ELD_SPEAKER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * drm_eld_get_conn_type - Get device type hdmi/dp connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * @eld: pointer to an ELD memory structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * The caller need to use %DRM_ELD_CONN_TYPE_HDMI or %DRM_ELD_CONN_TYPE_DP to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * identify the display type connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static inline u8 drm_eld_get_conn_type(const uint8_t *eld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_CONN_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) bool drm_probe_ddc(struct i2c_adapter *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct edid *drm_do_get_edid(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) size_t len),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct i2c_adapter *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) bool drm_detect_hdmi_monitor(struct edid *edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) enum hdmi_quantization_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) drm_default_rgb_quant_range(const struct drm_display_mode *mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) void drm_set_preferred_mode(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) int hpref, int vpref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) int drm_edid_header_is_valid(const u8 *raw_edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) bool *edid_corrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct drm_display_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) drm_display_mode_from_cea_vic(struct drm_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u8 video_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #ifdef CONFIG_DRM_EDID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct edid *drm_get_edid(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct i2c_adapter *adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct edid *drm_edid_duplicate(const struct edid *edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) int drm_add_override_edid_modes(struct drm_connector *connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) int drm_add_modes_noedid(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) int hdisplay, int vdisplay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) bool drm_detect_monitor_audio(struct edid *edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) void drm_edid_get_monitor_name(struct edid *edid, char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int buflen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) bool drm_edid_is_valid(struct edid *edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int hsize, int vsize, int fresh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) bool rb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static inline struct edid *drm_get_edid(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static inline struct edid *drm_edid_duplicate(const struct edid *edid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static inline int drm_add_edid_modes(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct edid *edid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static inline int drm_add_override_edid_modes(struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static inline u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static inline int drm_add_modes_noedid(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) int hdisplay, int vdisplay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static inline bool drm_detect_monitor_audio(struct edid *edid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static inline void drm_edid_get_monitor_name(struct edid *edid, char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) int buflen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static inline bool drm_edid_is_valid(struct edid *edid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static inline bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static inline struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) int hsize, int vsize, int fresh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) bool rb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #endif /* __DRM_EDID_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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