^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: MIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2018 Intel Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Manasi Navare <manasi.d.navare@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef DRM_DSC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define DRM_DSC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <drm/drm_dp_helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* VESA Display Stream Compression DSC 1.2 constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DSC_NUM_BUF_RANGES 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DSC_MUX_WORD_SIZE_8_10_BPC 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DSC_MUX_WORD_SIZE_12_BPC 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DSC_RC_PIXELS_PER_GROUP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DSC_SCALE_DECREMENT_INTERVAL_MAX 4095
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DSC_RANGE_BPG_OFFSET_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* DSC Rate Control Constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DSC_RC_MODEL_SIZE_CONST 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DSC_RC_EDGE_FACTOR_CONST 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DSC_RC_TGT_OFFSET_HI_CONST 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DSC_RC_TGT_OFFSET_LO_CONST 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* DSC PPS constants and macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DSC_PPS_VERSION_MAJOR_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DSC_PPS_BPC_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DSC_PPS_MSB_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DSC_PPS_LSB_MASK (0xFF << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DSC_PPS_BPP_HIGH_MASK (0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DSC_PPS_VBR_EN_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DSC_PPS_SIMPLE422_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DSC_PPS_CONVERT_RGB_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DSC_PPS_BLOCK_PRED_EN_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK (0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DSC_PPS_SCALE_DEC_INT_HIGH_MASK (0xF << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DSC_PPS_RC_TGT_OFFSET_HI_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DSC_PPS_RC_RANGE_MINQP_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DSC_PPS_NATIVE_420_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * This defines different rate control parameters used by the DSC engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * to compress the frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct drm_dsc_rc_range_parameters {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @range_min_qp: Min Quantization Parameters allowed for this range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u8 range_min_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @range_max_qp: Max Quantization Parameters allowed for this range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 range_max_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @range_bpg_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Bits/group offset to apply to target for this group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u8 range_bpg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * struct drm_dsc_config - Parameters required to configure DSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Driver populates this structure with all the parameters required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * to configure the display stream compression on the source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct drm_dsc_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @line_buf_depth:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Bits per component for previous reconstructed line buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 line_buf_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @bits_per_component: Bits per component to code (8/10/12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 bits_per_component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @convert_rgb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Flag to indicate if RGB - YCoCg conversion is needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * True if RGB input, False if YCoCg input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) bool convert_rgb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @slice_count: Number fo slices per line used by the DSC encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u8 slice_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @slice_width: Width of each slice in pixels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u16 slice_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @slice_height: Slice height in pixels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u16 slice_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @simple_422: True if simple 4_2_2 mode is enabled else False
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) bool simple_422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @pic_width: Width of the input display frame in pixels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u16 pic_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @pic_height: Vertical height of the input display frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u16 pic_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @rc_tgt_offset_high:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Offset to bits/group used by RC to determine QP adjustment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u8 rc_tgt_offset_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @rc_tgt_offset_low:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Offset to bits/group used by RC to determine QP adjustment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u8 rc_tgt_offset_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * @bits_per_pixel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * Target bits per pixel with 4 fractional bits, bits_per_pixel << 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u16 bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @rc_edge_factor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * Factor to determine if an edge is present based on the bits produced
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u8 rc_edge_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * @rc_quant_incr_limit1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * Slow down incrementing once the range reaches this value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u8 rc_quant_incr_limit1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @rc_quant_incr_limit0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * Slow down incrementing once the range reaches this value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u8 rc_quant_incr_limit0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @initial_xmit_delay:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * Number of pixels to delay the initial transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u16 initial_xmit_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * @initial_dec_delay:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * Initial decoder delay, number of pixel times that the decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * accumulates data in its rate buffer before starting to decode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * and output pixels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u16 initial_dec_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @block_pred_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * True if block prediction is used to code any groups within the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * picture. False if BP not used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) bool block_pred_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @first_line_bpg_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * Number of additional bits allocated for each group on the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * line of slice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u8 first_line_bpg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * @initial_offset: Value to use for RC model offset at slice start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u16 initial_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @rc_buf_thresh: Thresholds defining each of the buffer ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @rc_range_params:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * Parameters for each of the RC ranges defined in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * &struct drm_dsc_rc_range_parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * @rc_model_size: Total size of RC model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u16 rc_model_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * @flatness_min_qp: Minimum QP where flatness information is sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u8 flatness_min_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @flatness_max_qp: Maximum QP where flatness information is sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u8 flatness_max_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * @initial_scale_value: Initial value for the scale factor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u8 initial_scale_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * @scale_decrement_interval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * Specifies number of group times between decrementing the scale factor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * at beginning of a slice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u16 scale_decrement_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * @scale_increment_interval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * Number of group times between incrementing the scale factor value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * used at the beginning of a slice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u16 scale_increment_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * @nfl_bpg_offset: Non first line BPG offset to be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u16 nfl_bpg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * @slice_bpg_offset: BPG offset used to enforce slice bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u16 slice_bpg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * @final_offset: Final RC linear transformation offset value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u16 final_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @vbr_enable: True if VBR mode is enabled, false if disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) bool vbr_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * @mux_word_size: Mux word size (in bits) for SSM mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u8 mux_word_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @slice_chunk_size:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * The (max) size in bytes of the "chunks" that are used in slice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * multiplexing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u16 slice_chunk_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * @rc_bits: Rate control buffer size in bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u16 rc_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * @dsc_version_minor: DSC minor version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u8 dsc_version_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * @dsc_version_major: DSC major version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u8 dsc_version_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * @native_422: True if Native 4:2:2 supported, else false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) bool native_422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * @native_420: True if Native 4:2:0 supported else false.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) bool native_420;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * @second_line_bpg_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * Additional bits/grp for seconnd line of slice for native 4:2:0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u8 second_line_bpg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * @nsl_bpg_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * Num of bits deallocated for each grp that is not in second line of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * slice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u16 nsl_bpg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * @second_line_offset_adj:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * Offset adjustment for second line in Native 4:2:0 mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u16 second_line_offset_adj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * The VESA DSC standard defines picture parameter set (PPS) which display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * stream compression encoders must communicate to decoders.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * The PPS fields that span over more than a byte should be stored in Big Endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct drm_dsc_picture_parameter_set {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * @dsc_version:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * PPS0[7:4] - dsc_version_major: Contains major version of DSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u8 dsc_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * @pps_identifier:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * PPS1[7:0] - Application specific identifier that can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * used to differentiate between different PPS tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u8 pps_identifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * @pps_reserved:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * PPS2[7:0]- RESERVED Byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u8 pps_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * @pps_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * PPS3[7:4] - bits_per_component: Bits per component for the original
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * pixels of the encoded picture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * allowed only when dsc_minor_version = 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u8 pps_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * @pps_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * PPS4[1:0] -These are the most significant 2 bits of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * compressed BPP bits_per_pixel[9:0] syntax element.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * PPS4[3] - simple_422: Indicates if decoder drops samples to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * reconstruct the 4:2:2 picture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * groups in picture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * PPS4[7:6] - Reseved bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u8 pps_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * @bits_per_pixel_low:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * PPS5[7:0] - This indicates the lower significant 8 bits of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * the compressed BPP bits_per_pixel[9:0] element.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u8 bits_per_pixel_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * @pic_height:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * within the raster.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) __be16 pic_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * @pic_width:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * the raster.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) __be16 pic_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * @slice_height:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) __be16 slice_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * @slice_width:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) __be16 slice_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * @chunk_size:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * that are used for slice multiplexing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) __be16 chunk_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * @initial_xmit_delay_high:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * PPS16[1:0] - Most Significant two bits of initial transmission delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * It specifies the number of pixel times that the encoder waits before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * transmitting data from its rate buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * PPS16[7:2] - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u8 initial_xmit_delay_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * @initial_xmit_delay_low:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * PPS17[7:0] - Least significant 8 bits of initial transmission delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u8 initial_xmit_delay_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * @initial_dec_delay:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * of pixel times that the decoder accumulates data in its rate buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * before starting to decode and output pixels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) __be16 initial_dec_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * @pps20_reserved:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * PPS20[7:0] - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u8 pps20_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * @initial_scale_value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * PPS21[5:0] - Initial rcXformScale factor used at beginning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * of a slice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * PPS21[7:6] - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u8 initial_scale_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * @scale_increment_interval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * the rcXformScale factor at end of a slice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) __be16 scale_increment_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * @scale_decrement_interval_high:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * PPS24[3:0] - Higher 4 bits indicating number of group times between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * decrementing the rcXformScale factor at beginning of a slice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * PPS24[7:4] - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u8 scale_decrement_interval_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * @scale_decrement_interval_low:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * PPS25[7:0] - Lower 8 bits of scale decrement interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u8 scale_decrement_interval_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * @pps26_reserved:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * PPS26[7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u8 pps26_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * @first_line_bpg_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * PPS27[4:0] - Number of additional bits that are allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * for each group on first line of a slice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * PPS27[7:5] - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u8 first_line_bpg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * @nfl_bpg_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * deallocated for each group for groups after the first line of slice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) __be16 nfl_bpg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * @slice_bpg_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * PPS30, PPS31[7:0] - Number of bits that are deallocated for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * group to enforce the slice constraint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) __be16 slice_bpg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * @initial_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * PPS32,33[7:0] - Initial value for rcXformOffset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) __be16 initial_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * @final_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) __be16 final_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * @flatness_min_qp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * PPS36[4:0] - Minimum QP at which flatness is signaled and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * flatness QP adjustment is made.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * PPS36[7:5] - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u8 flatness_min_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * @flatness_max_qp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * PPS37[4:0] - Max QP at which flatness is signalled and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * the flatness adjustment is made.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * PPS37[7:5] - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u8 flatness_max_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * @rc_model_size:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * PPS38,39[7:0] - Number of bits within RC Model.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) __be16 rc_model_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * @rc_edge_factor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * PPS40[3:0] - Ratio of current activity vs, previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * activity to determine presence of edge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * PPS40[7:4] - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u8 rc_edge_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * @rc_quant_incr_limit0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * PPS41[4:0] - QP threshold used in short term RC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * PPS41[7:5] - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u8 rc_quant_incr_limit0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * @rc_quant_incr_limit1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * PPS42[4:0] - QP threshold used in short term RC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * PPS42[7:5] - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u8 rc_quant_incr_limit1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * @rc_tgt_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * PPS43[3:0] - Lower end of the variability range around the target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * bits per group that is allowed by short term RC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * PPS43[7:4]- Upper end of the variability range around the target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * bits per group that i allowed by short term rc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u8 rc_tgt_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * @rc_buf_thresh:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * the 15 ranges defined by 14 thresholds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * @rc_range_parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * PPS58[7:0] - PPS87[7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * Parameters that correspond to each of the 15 ranges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) __be16 rc_range_parameters[DSC_NUM_BUF_RANGES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * @native_422_420:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * PPS88[0] - 0 = Native 4:2:2 not used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * 1 = Native 4:2:2 used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * PPS88[1] - 0 = Native 4:2:0 not use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * 1 = Native 4:2:0 used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * PPS88[7:2] - Reserved 6 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u8 native_422_420;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * @second_line_bpg_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * PPS89[4:0] - Additional bits/group budget for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * second line of a slice in Native 4:2:0 mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * Set to 0 if DSC minor version is 1 or native420 is 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * PPS89[7:5] - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u8 second_line_bpg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * @nsl_bpg_offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * for each group that is not in the second line of a slice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) __be16 nsl_bpg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * @second_line_offset_adj:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * line in Native 4:2:0 mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) __be16 second_line_offset_adj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * @pps_long_94_reserved:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * PPS 94, 95, 96, 97 - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u32 pps_long_94_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * @pps_long_98_reserved:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * PPS 98, 99, 100, 101 - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) u32 pps_long_98_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * @pps_long_102_reserved:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * PPS 102, 103, 104, 105 - Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 pps_long_102_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * @pps_long_106_reserved:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * PPS 106, 107, 108, 109 - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u32 pps_long_106_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * @pps_long_110_reserved:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * PPS 110, 111, 112, 113 - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u32 pps_long_110_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * @pps_long_114_reserved:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * PPS 114 - 117 - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u32 pps_long_114_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * @pps_long_118_reserved:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * PPS 118 - 121 - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u32 pps_long_118_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * @pps_long_122_reserved:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * PPS 122- 125 - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u32 pps_long_122_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * @pps_short_126_reserved:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * PPS 126, 127 - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) __be16 pps_short_126_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture Parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * Set Metadata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * This structure represents the DSC PPS infoframe required to send the Picture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * Parameter Set metadata required before enabling VESA Display Stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * Compression. This is based on the DP Secondary Data Packet structure and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * comprises of SDP Header as defined &struct dp_sdp_header in drm_dp_helper.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * and PPS payload defined in &struct drm_dsc_picture_parameter_set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * @pps_header: Header for PPS as per DP SDP header format of type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * &struct dp_sdp_header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * @pps_payload: PPS payload fields as per DSC specification Table 4-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * as represented in &struct drm_dsc_picture_parameter_set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct drm_dsc_pps_infoframe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct dp_sdp_header pps_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct drm_dsc_picture_parameter_set pps_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) const struct drm_dsc_config *dsc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #endif /* _DRM_DSC_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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