^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright © 2008 Keith Packard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Permission to use, copy, modify, distribute, and sell this software and its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * documentation for any purpose is hereby granted without fee, provided that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * the above copyright notice appear in all copies and that both that copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * notice and this permission notice appear in supporting documentation, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * that the name of the copyright holders not be used in advertising or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * publicity pertaining to distribution of the software without specific,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * written prior permission. The copyright holders make no representations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * about the suitability of this software for any purpose. It is provided "as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * is" without express or implied warranty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OF THIS SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #ifndef _DRM_DP_HELPER_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define _DRM_DP_HELPER_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <drm/drm_connector.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct drm_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * DP and DPCD versions are independent. Differences from 1.0 are not noted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * 1.0 devices basically don't exist in the wild.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Abbreviations, in chronological order:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * eDP: Embedded DisplayPort version 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * DPI: DisplayPort Interoperability Guideline v1.1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * 1.2: DisplayPort 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * MST: Multistream Transport - part of DP 1.2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * 1.2 formally includes both eDP and DPI definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* MSA (Main Stream Attribute) MISC bits (as MISC1<<8|MISC0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DP_MSA_MISC_STEREO_PROG_LEFT_EYE (3 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* bits per component for non-RAW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DP_MSA_MISC_6_BPC (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DP_MSA_MISC_8_BPC (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DP_MSA_MISC_10_BPC (2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DP_MSA_MISC_12_BPC (3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DP_MSA_MISC_16_BPC (4 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* bits per component for RAW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DP_MSA_MISC_RAW_6_BPC (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DP_MSA_MISC_RAW_7_BPC (2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DP_MSA_MISC_RAW_8_BPC (3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DP_MSA_MISC_RAW_10_BPC (4 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DP_MSA_MISC_RAW_12_BPC (5 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DP_MSA_MISC_RAW_14_BPC (6 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DP_MSA_MISC_RAW_16_BPC (7 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* pixel encoding/colorimetry format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DP_MSA_MISC_COLOR_VSC_SDP (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DP_AUX_MAX_PAYLOAD_BYTES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DP_AUX_I2C_WRITE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DP_AUX_I2C_READ 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DP_AUX_I2C_MOT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DP_AUX_NATIVE_WRITE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DP_AUX_NATIVE_READ 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* AUX CH addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* DPCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DP_DPCD_REV 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) # define DP_DPCD_REV_10 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) # define DP_DPCD_REV_11 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) # define DP_DPCD_REV_12 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) # define DP_DPCD_REV_13 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) # define DP_DPCD_REV_14 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DP_MAX_LINK_RATE 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DP_MAX_LANE_COUNT 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) # define DP_MAX_LANE_COUNT_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) # define DP_ENHANCED_FRAME_CAP (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DP_MAX_DOWNSPREAD 0x003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) # define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) # define DP_TPS4_SUPPORTED (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DP_NORP 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DP_DOWNSTREAMPORT_PRESENT 0x005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) # define DP_DWN_STRM_PORT_PRESENT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) # define DP_DWN_STRM_PORT_TYPE_MASK 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) # define DP_FORMAT_CONVERSION (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DP_MAIN_LINK_CHANNEL_CODING 0x006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) # define DP_CAP_ANSI_8B10B (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DP_DOWN_STREAM_PORT_COUNT 0x007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) # define DP_PORT_COUNT_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) # define DP_OUI_SUPPORT (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DP_RECEIVE_PORT_0_CAP_0 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) # define DP_LOCAL_EDID_PRESENT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DP_RECEIVE_PORT_1_CAP_0 0x00a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DP_I2C_SPEED_CAP 0x00c /* DPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) # define DP_I2C_SPEED_1K 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) # define DP_I2C_SPEED_5K 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) # define DP_I2C_SPEED_10K 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) # define DP_I2C_SPEED_100K 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) # define DP_I2C_SPEED_400K 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) # define DP_I2C_SPEED_1M 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) # define DP_FRAMING_CHANGE_CAP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) # define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) # define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DP_ADAPTER_CAP 0x00f /* 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) # define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Multiple stream transport */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define DP_FAUX_CAP 0x020 /* 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) # define DP_FAUX_CAP_1 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define DP_MSTM_CAP 0x021 /* 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) # define DP_MST_CAP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* AV_SYNC_DATA_BLOCK 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define DP_AV_GRANULARITY 0x023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) # define DP_AG_FACTOR_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) # define DP_AG_FACTOR_3MS (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) # define DP_AG_FACTOR_2MS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) # define DP_AG_FACTOR_1MS (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) # define DP_AG_FACTOR_500US (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) # define DP_AG_FACTOR_200US (4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) # define DP_AG_FACTOR_100US (5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) # define DP_AG_FACTOR_10US (6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) # define DP_AG_FACTOR_1US (7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) # define DP_VG_FACTOR_MASK (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) # define DP_VG_FACTOR_3MS (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) # define DP_VG_FACTOR_2MS (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) # define DP_VG_FACTOR_1MS (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) # define DP_VG_FACTOR_500US (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) # define DP_VG_FACTOR_200US (4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) # define DP_VG_FACTOR_100US (5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define DP_AUD_DEC_LAT0 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define DP_AUD_DEC_LAT1 0x025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define DP_AUD_PP_LAT0 0x026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define DP_AUD_PP_LAT1 0x027
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define DP_VID_INTER_LAT 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define DP_VID_PROG_LAT 0x029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DP_REP_LAT 0x02a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define DP_AUD_DEL_INS0 0x02b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define DP_AUD_DEL_INS1 0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define DP_AUD_DEL_INS2 0x02d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* End of AV_SYNC_DATA_BLOCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) # define DP_ALPM_CAP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) # define DP_AUX_FRAME_SYNC_CAP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define DP_GUID 0x030 /* 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define DP_DSC_REV 0x061
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) # define DP_DSC_MAJOR_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) # define DP_DSC_MINOR_MASK (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) # define DP_DSC_MAJOR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) # define DP_DSC_MINOR_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define DP_DSC_RC_BUF_BLK_SIZE 0x062
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) # define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) # define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) # define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) # define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define DP_DSC_RC_BUF_SIZE 0x063
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define DP_DSC_SLICE_CAP_1 0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) # define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) # define DP_DSC_2_PER_DP_DSC_SINK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) # define DP_DSC_4_PER_DP_DSC_SINK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) # define DP_DSC_6_PER_DP_DSC_SINK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) # define DP_DSC_8_PER_DP_DSC_SINK (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) # define DP_DSC_10_PER_DP_DSC_SINK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) # define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) # define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) # define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) # define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) # define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) # define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) # define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) # define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) # define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) # define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) # define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) # define DP_DSC_RGB (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) # define DP_DSC_YCbCr444 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) # define DP_DSC_YCbCr422_Simple (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) # define DP_DSC_YCbCr422_Native (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) # define DP_DSC_YCbCr420_Native (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) # define DP_DSC_8_BPC (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) # define DP_DSC_10_BPC (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) # define DP_DSC_12_BPC (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define DP_DSC_PEAK_THROUGHPUT 0x06B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) # define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) # define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) # define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) # define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) # define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) # define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) # define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) # define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) # define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) # define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) # define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) # define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) # define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) # define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) # define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) # define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) # define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) # define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) # define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) # define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) # define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) # define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) # define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) # define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) # define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) # define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) # define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) # define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) # define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) # define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) # define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) # define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) # define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) # define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) # define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) # define DP_DSC_THROUGHPUT_MODE_1_170 (15 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define DP_DSC_MAX_SLICE_WIDTH 0x06C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define DP_DSC_SLICE_WIDTH_MULTIPLIER 320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define DP_DSC_SLICE_CAP_2 0x06D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) # define DP_DSC_20_PER_DP_DSC_SINK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define DP_DSC_BITS_PER_PIXEL_INC 0x06F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) # define DP_DSC_BITS_PER_PIXEL_1_16 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) # define DP_DSC_BITS_PER_PIXEL_1_8 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) # define DP_DSC_BITS_PER_PIXEL_1_4 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) # define DP_DSC_BITS_PER_PIXEL_1_2 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) # define DP_DSC_BITS_PER_PIXEL_1 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) # define DP_PSR_IS_SUPPORTED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) # define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define DP_PSR_CAPS 0x071 /* XXX 1.2? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) # define DP_PSR_NO_TRAIN_ON_EXIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) # define DP_PSR_SETUP_TIME_330 (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) # define DP_PSR_SETUP_TIME_275 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) # define DP_PSR_SETUP_TIME_220 (2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) # define DP_PSR_SETUP_TIME_165 (3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) # define DP_PSR_SETUP_TIME_110 (4 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) # define DP_PSR_SETUP_TIME_55 (5 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) # define DP_PSR_SETUP_TIME_0 (6 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) # define DP_PSR_SETUP_TIME_MASK (7 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) # define DP_PSR_SETUP_TIME_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) # define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) # define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * 0x80-0x8f describe downstream port capabilities, but there are two layouts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * each port's descriptor is one byte wide. If it was set, each port's is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * four bytes wide, starting with the one byte from the base info. As of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * DP interop v1.1a only VGA defines additional detail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* offset 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define DP_DOWNSTREAM_PORT_0 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) # define DP_DS_PORT_TYPE_MASK (7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) # define DP_DS_PORT_TYPE_DP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) # define DP_DS_PORT_TYPE_VGA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) # define DP_DS_PORT_TYPE_DVI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) # define DP_DS_PORT_TYPE_HDMI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) # define DP_DS_PORT_TYPE_NON_EDID 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) # define DP_DS_PORT_TYPE_DP_DUALMODE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) # define DP_DS_PORT_TYPE_WIRELESS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) # define DP_DS_PORT_HPD (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) # define DP_DS_NON_EDID_MASK (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) # define DP_DS_NON_EDID_720x480i_60 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) # define DP_DS_NON_EDID_720x480i_50 (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) # define DP_DS_NON_EDID_1920x1080i_60 (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) # define DP_DS_NON_EDID_1920x1080i_50 (4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) # define DP_DS_NON_EDID_1280x720_60 (5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) # define DP_DS_NON_EDID_1280x720_50 (7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* offset 1 for VGA is maximum megapixels per second / 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* offset 1 for DVI/HDMI is maximum TMDS clock in Mbps / 2.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* offset 2 for VGA/DVI/HDMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) # define DP_DS_MAX_BPC_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) # define DP_DS_8BPC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) # define DP_DS_10BPC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) # define DP_DS_12BPC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) # define DP_DS_16BPC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* offset 3 for DVI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) # define DP_DS_DVI_DUAL_LINK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) # define DP_DS_DVI_HIGH_COLOR_DEPTH (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* offset 3 for HDMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) # define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) # define DP_DS_HDMI_YCBCR422_PASS_THROUGH (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) # define DP_DS_HDMI_YCBCR420_PASS_THROUGH (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) # define DP_DS_HDMI_YCBCR444_TO_422_CONV (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) # define DP_DS_HDMI_YCBCR444_TO_420_CONV (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define DP_MAX_DOWNSTREAM_PORTS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* DP Forward error Correction Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define DP_FEC_CAPABILITY 0x090 /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) # define DP_FEC_CAPABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* DP Extended DSC Capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* link configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define DP_LINK_BW_SET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) # define DP_LINK_BW_1_62 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) # define DP_LINK_BW_2_7 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) # define DP_LINK_BW_5_4 0x14 /* 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) # define DP_LINK_BW_8_1 0x1e /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define DP_LANE_COUNT_SET 0x101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) # define DP_LANE_COUNT_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define DP_TRAINING_PATTERN_SET 0x102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) # define DP_TRAINING_PATTERN_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) # define DP_TRAINING_PATTERN_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) # define DP_TRAINING_PATTERN_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) # define DP_TRAINING_PATTERN_3 3 /* 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) # define DP_TRAINING_PATTERN_4 7 /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) # define DP_TRAINING_PATTERN_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) # define DP_TRAINING_PATTERN_MASK_1_4 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) # define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define DP_TRAINING_LANE0_SET 0x103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define DP_TRAINING_LANE1_SET 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define DP_TRAINING_LANE2_SET 0x105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define DP_TRAINING_LANE3_SET 0x106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) # define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define DP_DOWNSPREAD_CTRL 0x107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) # define DP_SPREAD_AMP_0_5 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) # define DP_SET_ANSI_8B10B (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* bitmask as for DP_I2C_SPEED_CAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) # define DP_FRAMING_CHANGE_ENABLE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) # define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define DP_LINK_QUAL_LANE1_SET 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define DP_LINK_QUAL_LANE2_SET 0x10d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define DP_LINK_QUAL_LANE3_SET 0x10e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) # define DP_LINK_QUAL_PATTERN_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) # define DP_LINK_QUAL_PATTERN_D10_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) # define DP_LINK_QUAL_PATTERN_PRBS7 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) # define DP_LINK_QUAL_PATTERN_HBR2_EYE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) # define DP_LINK_QUAL_PATTERN_MASK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define DP_TRAINING_LANE0_1_SET2 0x10f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define DP_TRAINING_LANE2_3_SET2 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define DP_MSTM_CTRL 0x111 /* 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) # define DP_MST_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) # define DP_UP_REQ_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) # define DP_UPSTREAM_IS_SRC (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define DP_AUDIO_DELAY0 0x112 /* 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define DP_AUDIO_DELAY1 0x113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define DP_AUDIO_DELAY2 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) # define DP_LINK_RATE_SET_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) # define DP_LINK_RATE_SET_MASK (7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) # define DP_ALPM_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) # define DP_IRQ_HPD_ENABLE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) # define DP_PWR_NOT_NEEDED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define DP_FEC_CONFIGURATION 0x120 /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) # define DP_FEC_READY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) # define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) # define DP_FEC_ERR_COUNT_DIS (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) # define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) # define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) # define DP_FEC_BIT_ERROR_COUNT (3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) # define DP_FEC_LANE_SELECT_MASK (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) # define DP_FEC_LANE_0_SELECT (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) # define DP_FEC_LANE_1_SELECT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) # define DP_FEC_LANE_2_SELECT (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) # define DP_FEC_LANE_3_SELECT (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) # define DP_AUX_FRAME_SYNC_VALID (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define DP_DSC_ENABLE 0x160 /* DP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) # define DP_DECOMPRESSION_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) # define DP_PSR_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) # define DP_PSR_CRC_VERIFICATION (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) # define DP_PSR_FRAME_CAPTURE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) # define DP_PSR_SELECTIVE_UPDATE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) # define DP_PSR_ENABLE_PSR2 (1 << 6) /* eDP 1.4a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define DP_ADAPTER_CTRL 0x1a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define DP_BRANCH_DEVICE_CTRL 0x1a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define DP_PAYLOAD_ALLOCATE_SET 0x1c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define DP_SINK_COUNT 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* prior to 1.2 bit 7 was reserved mbz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) # define DP_SINK_CP_READY (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) # define DP_AUTOMATED_TEST_REQUEST (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) # define DP_CP_IRQ (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) # define DP_MCCS_IRQ (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) # define DP_SINK_SPECIFIC_IRQ (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define DP_LANE0_1_STATUS 0x202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define DP_LANE2_3_STATUS 0x203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) # define DP_LANE_CR_DONE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) # define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) # define DP_LANE_SYMBOL_LOCKED (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) DP_LANE_CHANNEL_EQ_DONE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) DP_LANE_SYMBOL_LOCKED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define DP_LANE_ALIGN_STATUS_UPDATED 0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define DP_INTERLANE_ALIGN_DONE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define DP_LINK_STATUS_UPDATED (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define DP_SINK_STATUS 0x205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define DP_RECEIVE_PORT_0_STATUS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define DP_RECEIVE_PORT_1_STATUS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define DP_ADJUST_REQUEST_LANE0_1 0x206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define DP_ADJUST_REQUEST_LANE2_3 0x207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) # define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) # define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) # define DP_ADJUST_POST_CURSOR2_LANE1_MASK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) # define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) # define DP_ADJUST_POST_CURSOR2_LANE2_MASK 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) # define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) # define DP_ADJUST_POST_CURSOR2_LANE3_MASK 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) # define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define DP_TEST_REQUEST 0x218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) # define DP_TEST_LINK_TRAINING (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) # define DP_TEST_LINK_EDID_READ (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) # define DP_TEST_LINK_AUDIO_PATTERN (1 << 5) /* DPCD >= 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) # define DP_TEST_LINK_AUDIO_DISABLED_VIDEO (1 << 6) /* DPCD >= 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define DP_TEST_LINK_RATE 0x219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) # define DP_LINK_RATE_162 (0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) # define DP_LINK_RATE_27 (0xa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define DP_TEST_LANE_COUNT 0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define DP_TEST_PATTERN 0x221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) # define DP_NO_TEST_PATTERN 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) # define DP_COLOR_RAMP 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) # define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) # define DP_COLOR_SQUARE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define DP_TEST_H_TOTAL_HI 0x222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define DP_TEST_H_TOTAL_LO 0x223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define DP_TEST_V_TOTAL_HI 0x224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define DP_TEST_V_TOTAL_LO 0x225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define DP_TEST_H_START_HI 0x226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define DP_TEST_H_START_LO 0x227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define DP_TEST_V_START_HI 0x228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define DP_TEST_V_START_LO 0x229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define DP_TEST_HSYNC_HI 0x22A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) # define DP_TEST_HSYNC_POLARITY (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) # define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define DP_TEST_HSYNC_WIDTH_LO 0x22B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define DP_TEST_VSYNC_HI 0x22C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) # define DP_TEST_VSYNC_POLARITY (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) # define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define DP_TEST_VSYNC_WIDTH_LO 0x22D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define DP_TEST_H_WIDTH_HI 0x22E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define DP_TEST_H_WIDTH_LO 0x22F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define DP_TEST_V_HEIGHT_HI 0x230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define DP_TEST_V_HEIGHT_LO 0x231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define DP_TEST_MISC0 0x232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) # define DP_TEST_SYNC_CLOCK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) # define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) # define DP_TEST_COLOR_FORMAT_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) # define DP_COLOR_FORMAT_RGB (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) # define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) # define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) # define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) # define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) # define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) # define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) # define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) # define DP_TEST_BIT_DEPTH_MASK (7 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) # define DP_TEST_BIT_DEPTH_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) # define DP_TEST_BIT_DEPTH_6 (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) # define DP_TEST_BIT_DEPTH_8 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) # define DP_TEST_BIT_DEPTH_10 (2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) # define DP_TEST_BIT_DEPTH_12 (3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) # define DP_TEST_BIT_DEPTH_16 (4 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define DP_TEST_MISC1 0x233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) # define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) # define DP_TEST_INTERLACED (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define DP_TEST_MISC0 0x232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define DP_TEST_CRC_R_CR 0x240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define DP_TEST_CRC_G_Y 0x242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define DP_TEST_CRC_B_CB 0x244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define DP_TEST_SINK_MISC 0x246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) # define DP_TEST_CRC_SUPPORTED (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) # define DP_TEST_COUNT_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define DP_PHY_TEST_PATTERN 0x248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) # define DP_PHY_TEST_PATTERN_SEL_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) # define DP_PHY_TEST_PATTERN_NONE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) # define DP_PHY_TEST_PATTERN_D10_2 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) # define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) # define DP_PHY_TEST_PATTERN_PRBS7 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) # define DP_PHY_TEST_PATTERN_CP2520 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define DP_TEST_RESPONSE 0x260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) # define DP_TEST_ACK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) # define DP_TEST_NAK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define DP_TEST_EDID_CHECKSUM 0x261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define DP_TEST_SINK 0x270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) # define DP_TEST_SINK_START (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define DP_TEST_AUDIO_MODE 0x271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define DP_TEST_AUDIO_PATTERN_TYPE 0x272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define DP_TEST_AUDIO_PERIOD_CH1 0x273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define DP_TEST_AUDIO_PERIOD_CH2 0x274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define DP_TEST_AUDIO_PERIOD_CH3 0x275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define DP_TEST_AUDIO_PERIOD_CH4 0x276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define DP_TEST_AUDIO_PERIOD_CH5 0x277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define DP_TEST_AUDIO_PERIOD_CH6 0x278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define DP_TEST_AUDIO_PERIOD_CH7 0x279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define DP_TEST_AUDIO_PERIOD_CH8 0x27A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define DP_FEC_STATUS 0x280 /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) # define DP_FEC_DECODE_EN_DETECTED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) # define DP_FEC_DECODE_DIS_DETECTED (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) # define DP_FEC_ERROR_COUNT_MASK 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) # define DP_FEC_ERR_COUNT_VALID (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) # define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) # define DP_PAYLOAD_ACT_HANDLED (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* up to ID_SLOT_63 at 0x2ff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define DP_SOURCE_OUI 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define DP_SINK_OUI 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define DP_BRANCH_OUI 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define DP_BRANCH_ID 0x503
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define DP_BRANCH_REVISION_START 0x509
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define DP_BRANCH_HW_REV 0x509
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define DP_BRANCH_SW_REV 0x50A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define DP_SET_POWER 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) # define DP_SET_POWER_D0 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) # define DP_SET_POWER_D3 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) # define DP_SET_POWER_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) # define DP_SET_POWER_D3_AUX_ON 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) # define DP_EDP_11 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) # define DP_EDP_12 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) # define DP_EDP_13 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) # define DP_EDP_14 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) # define DP_EDP_14a 0x04 /* eDP 1.4a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) # define DP_EDP_14b 0x05 /* eDP 1.4b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define DP_EDP_GENERAL_CAP_1 0x701
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) # define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) # define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) # define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) # define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) # define DP_EDP_FRC_ENABLE_CAP (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) # define DP_EDP_COLOR_ENGINE_CAP (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) # define DP_EDP_SET_POWER_CAP (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) # define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) # define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) # define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) # define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) # define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define DP_EDP_GENERAL_CAP_2 0x703
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) # define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) # define DP_EDP_X_REGION_CAP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) # define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) # define DP_EDP_Y_REGION_CAP_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) # define DP_EDP_BACKLIGHT_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) # define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) # define DP_EDP_FRC_ENABLE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) # define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) # define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) # define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) # define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) # define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) # define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) # define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define DP_EDP_PWMGEN_BIT_COUNT 0x724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) # define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define DP_EDP_BACKLIGHT_FREQ_SET 0x728
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) # define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /* 0-5 sink count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) # define DP_SINK_COUNT_CP_READY (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) # define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) # define DP_LOCK_ACQUISITION_REQUEST (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) # define DP_CEC_IRQ (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) # define DP_PSR_LINK_CRC_ERROR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) # define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define DP_PSR_ESI 0x2007 /* XXX 1.2? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) # define DP_PSR_CAPS_CHANGE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) # define DP_PSR_SINK_INACTIVE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) # define DP_PSR_SINK_ACTIVE_RFB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) # define DP_PSR_SINK_ACTIVE_RESYNC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) # define DP_PSR_SINK_INTERNAL_ERROR 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) # define DP_PSR_SINK_STATE_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) # define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) # define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) # define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) # define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) # define DP_SU_VALID (1 << 3) /* eDP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) # define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) # define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) # define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define DP_DP13_DPCD_REV 0x2200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define DP_DP13_MAX_LINK_RATE 0x2201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) # define DP_GTC_CAP (1 << 0) /* DP 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) # define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) # define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) # define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) # define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) # define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) # define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define DP_CEC_TUNNELING_CAPABILITY 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) # define DP_CEC_TUNNELING_CAPABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) # define DP_CEC_SNOOPING_CAPABLE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) # define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define DP_CEC_TUNNELING_CONTROL 0x3001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) # define DP_CEC_TUNNELING_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) # define DP_CEC_SNOOPING_ENABLE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define DP_CEC_RX_MESSAGE_INFO 0x3002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) # define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) # define DP_CEC_RX_MESSAGE_LEN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) # define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) # define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) # define DP_CEC_RX_MESSAGE_ACKED (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) # define DP_CEC_RX_MESSAGE_ENDED (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define DP_CEC_TX_MESSAGE_INFO 0x3003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) # define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) # define DP_CEC_TX_MESSAGE_LEN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) # define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) # define DP_CEC_TX_RETRY_COUNT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) # define DP_CEC_TX_MESSAGE_SEND (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) # define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) # define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) # define DP_CEC_TX_MESSAGE_SENT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) # define DP_CEC_TX_LINE_ERROR (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) # define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) # define DP_CEC_TX_DATA_NACK_ERROR (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) # define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) # define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) # define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) # define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) # define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) # define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) # define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) # define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) # define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) # define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) # define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) # define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) # define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) # define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) # define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) # define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define DP_CEC_RX_MESSAGE_BUFFER 0x3010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define DP_CEC_TX_MESSAGE_BUFFER 0x3020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define DP_PROTOCOL_CONVERTER_CONTROL_0 0x3050 /* DP 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) # define DP_HDMI_DVI_OUTPUT_CONFIG (1 << 0) /* DP 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define DP_PROTOCOL_CONVERTER_CONTROL_1 0x3051 /* DP 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) # define DP_CONVERSION_TO_YCBCR420_ENABLE (1 << 0) /* DP 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) # define DP_HDMI_EDID_PROCESSING_DISABLE (1 << 1) /* DP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) # define DP_HDMI_AUTONOMOUS_SCRAMBLING_DISABLE (1 << 2) /* DP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) # define DP_HDMI_FORCE_SCRAMBLING (1 << 3) /* DP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define DP_PROTOCOL_CONVERTER_CONTROL_2 0x3052 /* DP 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) # define DP_CONVERSION_TO_YCBCR422_ENABLE (1 << 0) /* DP 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define DP_AUX_HDCP_BKSV 0x68000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define DP_AUX_HDCP_RI_PRIME 0x68005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define DP_AUX_HDCP_AKSV 0x68007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define DP_AUX_HDCP_AN 0x6800C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define DP_AUX_HDCP_BCAPS 0x68028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) # define DP_BCAPS_REPEATER_PRESENT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) # define DP_BCAPS_HDCP_CAPABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define DP_AUX_HDCP_BSTATUS 0x68029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) # define DP_BSTATUS_REAUTH_REQ BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) # define DP_BSTATUS_LINK_FAILURE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) # define DP_BSTATUS_R0_PRIME_READY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) # define DP_BSTATUS_READY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define DP_AUX_HDCP_BINFO 0x6802A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define DP_AUX_HDCP_KSV_FIFO 0x6802C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define DP_AUX_HDCP_AINFO 0x6803B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /* DP HDCP2.2 parameter offsets in DPCD address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define DP_HDCP_2_2_REG_M_OFFSET 0x692B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define DP_HDCP_2_2_REG_V_OFFSET 0x693E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define DP_HDCP_2_2_REG_K_OFFSET 0x693F3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* Link Training (LT)-tunable PHY Repeaters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291 /* 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /* Repeater modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /* DP HDCP message start offsets in DPCD address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) #define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #define HDCP_2_2_DP_RXSTATUS_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) /* DP 1.2 Sideband message defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) /* peer device type - DP 1.2a Table 2-92 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) #define DP_PEER_DEVICE_NONE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) #define DP_PEER_DEVICE_MST_BRANCHING 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define DP_PEER_DEVICE_SST_SINK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) #define DP_GET_MSG_TRANSACTION_VERSION 0x00 /* DP 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define DP_LINK_ADDRESS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define DP_CONNECTION_STATUS_NOTIFY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define DP_ENUM_PATH_RESOURCES 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define DP_ALLOCATE_PAYLOAD 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) #define DP_QUERY_PAYLOAD 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) #define DP_RESOURCE_STATUS_NOTIFY 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #define DP_REMOTE_DPCD_READ 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define DP_REMOTE_DPCD_WRITE 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #define DP_REMOTE_I2C_READ 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define DP_REMOTE_I2C_WRITE 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define DP_POWER_UP_PHY 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #define DP_POWER_DOWN_PHY 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #define DP_SINK_EVENT_NOTIFY 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define DP_QUERY_STREAM_ENC_STATUS 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #define DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /* DP 1.2 MST sideband reply types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) #define DP_SIDEBAND_REPLY_ACK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #define DP_SIDEBAND_REPLY_NAK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* DP 1.2 MST sideband nak reasons - table 2.84 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #define DP_NAK_WRITE_FAILURE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define DP_NAK_INVALID_READ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define DP_NAK_CRC_FAILURE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define DP_NAK_BAD_PARAM 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define DP_NAK_DEFER 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define DP_NAK_LINK_FAILURE 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #define DP_NAK_NO_RESOURCES 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define DP_NAK_DPCD_FAIL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define DP_NAK_I2C_NAK 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define DP_NAK_ALLOCATE_FAIL 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define MODE_I2C_START 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define MODE_I2C_WRITE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define MODE_I2C_READ 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define MODE_I2C_STOP 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define DP_MST_PHYSICAL_PORT_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define DP_MST_LOGICAL_PORT_0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #define DP_LINK_CONSTANT_N_VALUE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define DP_LINK_STATUS_SIZE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) int lane_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) int lane_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) int lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) int lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) unsigned int lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #define DP_BRANCH_OUI_HEADER_SIZE 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define DP_RECEIVER_CAP_SIZE 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define DP_DSC_RECEIVER_CAP_SIZE 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define EDP_PSR_RECEIVER_CAP_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define EDP_DISPLAY_CTL_CAP_SIZE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) u8 drm_dp_link_rate_to_bw_code(int link_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) int drm_dp_bw_code_to_link_rate(u8 link_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define DP_SDP_AUDIO_TIMESTAMP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define DP_SDP_AUDIO_STREAM 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define DP_SDP_EXTENSION 0x04 /* DP 1.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define DP_SDP_ISRC 0x06 /* DP 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define DP_SDP_VSC 0x07 /* DP 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define DP_SDP_PPS 0x10 /* DP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /* 0x80+ CEA-861 infoframe types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * struct dp_sdp_header - DP secondary data packet header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) * @HB0: Secondary Data Packet ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) * @HB1: Secondary Data Packet Type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) * @HB2: Secondary Data Packet Specific header, Byte 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) * @HB3: Secondary Data packet Specific header, Byte 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct dp_sdp_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) u8 HB0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) u8 HB1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) u8 HB2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) u8 HB3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #define EDP_SDP_HEADER_REVISION_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) #define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * struct dp_sdp - DP secondary data packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * @sdp_header: DP secondary data packet header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) * @db: DP secondaray data packet data blocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) * VSC SDP Payload for PSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) * db[0]: Stereo Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * db[2]: CRC value bits 7:0 of the R or Cr component
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * db[3]: CRC value bits 15:8 of the R or Cr component
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * db[4]: CRC value bits 7:0 of the G or Y component
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * db[5]: CRC value bits 15:8 of the G or Y component
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) * db[6]: CRC value bits 7:0 of the B or Cb component
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) * db[7]: CRC value bits 15:8 of the B or Cb component
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) * db[8] - db[31]: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * VSC SDP Payload for Pixel Encoding/Colorimetry Format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) * db[0] - db[15]: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) * db[16]: Pixel Encoding and Colorimetry Formats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * db[17]: Dynamic Range and Component Bit Depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * db[18]: Content Type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * db[19] - db[31]: Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) struct dp_sdp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) struct dp_sdp_header sdp_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) u8 db[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define EDP_VSC_PSR_UPDATE_RFB (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) * enum dp_pixelformat - drm DP Pixel encoding formats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) * This enum is used to indicate DP VSC SDP Pixel encoding formats.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) * DB18]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) * @DP_PIXELFORMAT_RGB: RGB pixel encoding format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) * @DP_PIXELFORMAT_YUV444: YCbCr 4:4:4 pixel encoding format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * @DP_PIXELFORMAT_YUV422: YCbCr 4:2:2 pixel encoding format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) * @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) * @DP_PIXELFORMAT_Y_ONLY: Y Only pixel encoding format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) * @DP_PIXELFORMAT_RAW: RAW pixel encoding format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) * @DP_PIXELFORMAT_RESERVED: Reserved pixel encoding format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) enum dp_pixelformat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) DP_PIXELFORMAT_RGB = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) DP_PIXELFORMAT_YUV444 = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) DP_PIXELFORMAT_YUV422 = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) DP_PIXELFORMAT_YUV420 = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) DP_PIXELFORMAT_Y_ONLY = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) DP_PIXELFORMAT_RAW = 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) DP_PIXELFORMAT_RESERVED = 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) * enum dp_colorimetry - drm DP Colorimetry formats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) * This enum is used to indicate DP VSC SDP Colorimetry formats.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) * DB18] and a name of enum member follows DRM_MODE_COLORIMETRY definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) * @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) * ITU-R BT.601 colorimetry format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) * @DP_COLORIMETRY_RGB_WIDE_FIXED: RGB wide gamut fixed point colorimetry format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * @DP_COLORIMETRY_BT709_YCC: ITU-R BT.709 colorimetry format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * @DP_COLORIMETRY_RGB_WIDE_FLOAT: RGB wide gamut floating point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) * (scRGB (IEC 61966-2-2)) colorimetry format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) * @DP_COLORIMETRY_XVYCC_601: xvYCC601 colorimetry format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) * @DP_COLORIMETRY_OPRGB: OpRGB colorimetry format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) * @DP_COLORIMETRY_XVYCC_709: xvYCC709 colorimetry format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) * @DP_COLORIMETRY_DCI_P3_RGB: DCI-P3 (SMPTE RP 431-2) colorimetry format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) * @DP_COLORIMETRY_SYCC_601: sYCC601 colorimetry format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) * @DP_COLORIMETRY_RGB_CUSTOM: RGB Custom Color Profile colorimetry format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) * @DP_COLORIMETRY_OPYCC_601: opYCC601 colorimetry format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) * @DP_COLORIMETRY_BT2020_RGB: ITU-R BT.2020 R' G' B' colorimetry format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) * @DP_COLORIMETRY_BT2020_CYCC: ITU-R BT.2020 Y'c C'bc C'rc colorimetry format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) * @DP_COLORIMETRY_BT2020_YCC: ITU-R BT.2020 Y' C'b C'r colorimetry format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) enum dp_colorimetry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) DP_COLORIMETRY_DEFAULT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) DP_COLORIMETRY_BT709_YCC = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) DP_COLORIMETRY_XVYCC_601 = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) DP_COLORIMETRY_OPRGB = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) DP_COLORIMETRY_XVYCC_709 = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) DP_COLORIMETRY_DCI_P3_RGB = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) DP_COLORIMETRY_SYCC_601 = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) DP_COLORIMETRY_RGB_CUSTOM = 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) DP_COLORIMETRY_OPYCC_601 = 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) DP_COLORIMETRY_BT2020_RGB = 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) DP_COLORIMETRY_BT2020_CYCC = 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) DP_COLORIMETRY_BT2020_YCC = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) * enum dp_dynamic_range - drm DP Dynamic Range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) * This enum is used to indicate DP VSC SDP Dynamic Range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) * DB18]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * @DP_DYNAMIC_RANGE_VESA: VESA range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) * @DP_DYNAMIC_RANGE_CTA: CTA range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) enum dp_dynamic_range {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) DP_DYNAMIC_RANGE_VESA = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) DP_DYNAMIC_RANGE_CTA = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) * enum dp_content_type - drm DP Content Type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) * This enum is used to indicate DP VSC SDP Content Types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) * DB18]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) * CTA-861-G defines content types and expected processing by a sink device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * @DP_CONTENT_TYPE_NOT_DEFINED: Not defined type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * @DP_CONTENT_TYPE_GRAPHICS: Graphics type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * @DP_CONTENT_TYPE_PHOTO: Photo type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * @DP_CONTENT_TYPE_VIDEO: Video type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) * @DP_CONTENT_TYPE_GAME: Game type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) enum dp_content_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) DP_CONTENT_TYPE_GRAPHICS = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) DP_CONTENT_TYPE_PHOTO = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) DP_CONTENT_TYPE_VIDEO = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) DP_CONTENT_TYPE_GAME = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) * struct drm_dp_vsc_sdp - drm DP VSC SDP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * This structure represents a DP VSC SDP of drm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) * [Table 2-117: VSC SDP Payload for DB16 through DB18]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) * @sdp_type: secondary-data packet type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) * @revision: revision number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) * @length: number of valid data bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) * @pixelformat: pixel encoding format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) * @colorimetry: colorimetry format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) * @bpc: bit per color
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) * @dynamic_range: dynamic range information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) * @content_type: CTA-861-G defines content types and expected processing by a sink device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) struct drm_dp_vsc_sdp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) unsigned char sdp_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) unsigned char revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) unsigned char length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) enum dp_pixelformat pixelformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) enum dp_colorimetry colorimetry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) int bpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) enum dp_dynamic_range dynamic_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) enum dp_content_type content_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) const struct drm_dp_vsc_sdp *vsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) static inline u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) static inline bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) return dpcd[DP_DPCD_REV] >= 0x11 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) static inline bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) return dpcd[DP_DPCD_REV] >= 0x11 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) static inline bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return dpcd[DP_DPCD_REV] >= 0x12 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) static inline bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return dpcd[DP_DPCD_REV] >= 0x14 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) static inline u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) DP_TRAINING_PATTERN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) static inline bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) /* DP/eDP DSC support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) bool is_edp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) u8 dsc_bpc[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) static inline bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) DP_DSC_DECOMPRESSION_IS_SUPPORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) static inline u16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static inline u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) /* Max Slicewidth = Number of Pixels * 320 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) DP_DSC_SLICE_WIDTH_MULTIPLIER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) /* Forward Error Correction Support on DP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) static inline bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) drm_dp_sink_supports_fec(const u8 fec_capable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) return fec_capable & DP_FEC_CAPABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) static inline bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) static inline bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) return dpcd[DP_EDP_CONFIGURATION_CAP] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) DP_ALTERNATE_SCRAMBLER_RESET_CAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) /* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) static inline bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) DP_MSA_TIMING_PAR_IGNORED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) * DisplayPort AUX channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) * @address: address of the (first) register to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) * @request: contains the type of transaction (see DP_AUX_* macros)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) * @reply: upon completion, contains the reply type of the transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) * @buffer: pointer to a transmission or reception buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) * @size: size of @buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) struct drm_dp_aux_msg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) unsigned int address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) u8 request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) u8 reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) void *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) struct cec_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) struct edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) struct drm_connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) * @lock: mutex protecting this struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) * @connector: the connector this CEC adapter is associated with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) * @unregister_work: unregister the CEC adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) struct drm_dp_aux_cec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) struct cec_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) struct drm_connector *connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) struct delayed_work unregister_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) * struct drm_dp_aux - DisplayPort AUX channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) * @ddc: I2C adapter that can be used for I2C-over-AUX communication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) * @dev: pointer to struct device that is the parent for this AUX channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) * @crtc: backpointer to the crtc that is currently using this AUX channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) * @hw_mutex: internal mutex used for locking transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) * @crc_work: worker that captures CRCs for each frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) * @crc_count: counter of captured frame CRCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) * @transfer: transfers a message representing a single AUX transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) * The .dev field should be set to a pointer to the device that implements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) * the AUX channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) * The .name field may be used to specify the name of the I2C adapter. If set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) * NULL, dev_name() of .dev will be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) * Drivers provide a hardware-specific implementation of how transactions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) * structure describing the transaction is passed into this function. Upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) * success, the implementation should return the number of payload bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) * that were transferred, or a negative error-code on failure. Helpers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) * propagate errors from the .transfer() function, with the exception of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) * the -EBUSY error, which causes a transaction to be retried. On a short,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) * helpers will return -EPROTO to make it simpler to check for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) * An AUX channel can also be used to transport I2C messages to a sink. A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) * typical application of that is to access an EDID that's present in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) * sink device. The .transfer() function can also be used to execute such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) * transactions. The drm_dp_aux_register() function registers an I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) * adapter that can be passed to drm_probe_ddc(). Upon removal, drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) * should call drm_dp_aux_unregister() to remove the I2C adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) * The I2C adapter uses long transfers by default; if a partial response is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) * received, the adapter will drop down to the size given by the partial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) * response for this transaction only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) * Note that the aux helper code assumes that the .transfer() function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) * only modifies the reply field of the drm_dp_aux_msg structure. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) * retry logic and i2c helpers assume this is the case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) struct drm_dp_aux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) struct i2c_adapter ddc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) struct drm_crtc *crtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) struct mutex hw_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) struct work_struct crc_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) u8 crc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) ssize_t (*transfer)(struct drm_dp_aux *aux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) struct drm_dp_aux_msg *msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) unsigned i2c_nack_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) unsigned i2c_defer_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) struct drm_dp_aux_cec cec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) * @is_remote: Is this AUX CH actually using sideband messaging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) bool is_remote;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) void *buffer, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) void *buffer, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) * drm_dp_dpcd_readb() - read a single byte from the DPCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) * @aux: DisplayPort AUX channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) * @offset: address of the register to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) * @valuep: location where the value of the register will be stored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) * Returns the number of bytes transferred (1) on success, or a negative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) * error code on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) unsigned int offset, u8 *valuep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) return drm_dp_dpcd_read(aux, offset, valuep, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) * drm_dp_dpcd_writeb() - write a single byte to the DPCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) * @aux: DisplayPort AUX channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) * @offset: address of the register to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) * @value: value to write to the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) * Returns the number of bytes transferred (1) on success, or a negative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) * error code on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) unsigned int offset, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) return drm_dp_dpcd_write(aux, offset, &value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) u8 dpcd[DP_RECEIVER_CAP_SIZE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) u8 status[DP_LINK_STATUS_SIZE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) u8 real_edid_checksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) const u8 dpcd[DP_RECEIVER_CAP_SIZE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) const u8 port_cap[4], u8 type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) const u8 port_cap[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) const struct edid *edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) const u8 port_cap[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) const u8 port_cap[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) const struct edid *edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) const u8 port_cap[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) const struct edid *edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) const u8 port_cap[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) const struct edid *edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) const u8 port_cap[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) const u8 port_cap[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) const u8 dpcd[DP_RECEIVER_CAP_SIZE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) const u8 port_cap[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) void drm_dp_downstream_debug(struct seq_file *m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) const u8 dpcd[DP_RECEIVER_CAP_SIZE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) const u8 port_cap[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) const struct edid *edid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) struct drm_dp_aux *aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) enum drm_mode_subconnector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) const u8 port_cap[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) void drm_dp_set_subconnector_property(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) enum drm_connector_status status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) const u8 *dpcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) const u8 port_cap[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) struct drm_dp_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) const u8 dpcd[DP_RECEIVER_CAP_SIZE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) const struct drm_dp_desc *desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) int drm_dp_read_sink_count(struct drm_dp_aux *aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) void drm_dp_aux_init(struct drm_dp_aux *aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) int drm_dp_aux_register(struct drm_dp_aux *aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) void drm_dp_aux_unregister(struct drm_dp_aux *aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) int drm_dp_stop_crc(struct drm_dp_aux *aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) struct drm_dp_dpcd_ident {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) u8 oui[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) u8 device_id[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) u8 hw_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) u8 sw_major_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) u8 sw_minor_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) * struct drm_dp_desc - DP branch/sink device descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) struct drm_dp_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) struct drm_dp_dpcd_ident ident;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) u32 quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) bool is_branch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) u32 drm_dp_get_edid_quirks(const struct edid *edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) * enum drm_dp_quirk - Display Port sink/branch device specific quirks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) * Display Port sink and branch devices in the wild have a variety of bugs, try
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) * to collect them here. The quirks are shared, but it's up to the drivers to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) * implement workarounds for them. Note that because some devices have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) * unreliable OUIDs, the EDID of sinks should also be checked for quirks using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) * drm_dp_get_edid_quirks().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) enum drm_dp_quirk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) * @DP_DPCD_QUIRK_CONSTANT_N:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) * The device requires main link attributes Mvid and Nvid to be limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) * to 16 bits. So will give a constant value (0x8000) for compatability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) DP_DPCD_QUIRK_CONSTANT_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) * @DP_DPCD_QUIRK_NO_PSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) * The device does not support PSR even if reports that it supports or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) * driver still need to implement proper handling for such device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) DP_DPCD_QUIRK_NO_PSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) * @DP_DPCD_QUIRK_NO_SINK_COUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) * The device does not set SINK_COUNT to a non-zero value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) * The driver should ignore SINK_COUNT during detection. Note that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) * drm_dp_read_sink_count_cap() automatically checks for this quirk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) DP_DPCD_QUIRK_NO_SINK_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) * The device supports MST DSC despite not supporting Virtual DPCD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) * The DSC caps can be read from the physical aux instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) * @DP_QUIRK_FORCE_DPCD_BACKLIGHT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) * The device is telling the truth when it says that it uses DPCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) * backlight controls, even if the system's firmware disagrees. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) * quirk should be checked against both the ident and panel EDID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) * When present, the driver should honor the DPCD backlight
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) * capabilities advertised.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) DP_QUIRK_FORCE_DPCD_BACKLIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) * the DP_MAX_LINK_RATE register reporting a lower max multiplier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) * drm_dp_has_quirk() - does the DP device have a specific quirk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) * @desc: Device descriptor filled by drm_dp_read_desc()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) * @edid_quirks: Optional quirk bitmask filled by drm_dp_get_edid_quirks()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) * @quirk: Quirk to query for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) * Return true if DP device identified by @desc has @quirk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) static inline bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) drm_dp_has_quirk(const struct drm_dp_desc *desc, u32 edid_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) enum drm_dp_quirk quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) return (desc->quirks | edid_quirks) & BIT(quirk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) #ifdef CONFIG_DRM_DP_CEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) void drm_dp_cec_irq(struct drm_dp_aux *aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) struct drm_connector *connector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) drm_dp_cec_register_connector(struct drm_dp_aux *aux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) struct drm_connector *connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) const struct edid *edid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) * struct drm_dp_phy_test_params - DP Phy Compliance parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) * @link_rate: Requested Link rate from DPCD 0x219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) * @num_lanes: Number of lanes requested by sing through DPCD 0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) * @phy_pattern: DP Phy test pattern from DPCD 0x248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) * @enhanced_frame_cap: flag for enhanced frame capability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) struct drm_dp_phy_test_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) int link_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) u8 num_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) u8 phy_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) u8 hbr2_reset[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) u8 custom80[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) bool enhanced_frame_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) struct drm_dp_phy_test_params *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) struct drm_dp_phy_test_params *data, u8 dp_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) #endif /* _DRM_DP_HELPER_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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