^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Defines for Mobile High-Definition Link (MHL) interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015, Samsung Electronics, Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Andrzej Hajda <a.hajda@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on MHL driver for Android devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2013-2014 Silicon Image, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __MHL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __MHL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Device Capabilities Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) MHL_DCAP_DEV_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) MHL_DCAP_MHL_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MHL_DCAP_CAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MHL_DCAP_ADOPTER_ID_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MHL_DCAP_ADOPTER_ID_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MHL_DCAP_VID_LINK_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MHL_DCAP_AUD_LINK_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MHL_DCAP_VIDEO_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MHL_DCAP_LOG_DEV_MAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MHL_DCAP_BANDWIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MHL_DCAP_FEATURE_FLAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MHL_DCAP_DEVICE_ID_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MHL_DCAP_DEVICE_ID_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MHL_DCAP_SCRATCHPAD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MHL_DCAP_INT_STAT_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MHL_DCAP_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MHL_DCAP_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MHL_DCAP_CAT_SINK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MHL_DCAP_CAT_SOURCE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MHL_DCAP_CAT_POWER 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MHL_DCAP_CAT_PLIM(x) ((x) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MHL_DCAP_VID_LINK_RGB444 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MHL_DCAP_VID_LINK_YCBCR444 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MHL_DCAP_VID_LINK_YCBCR422 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MHL_DCAP_VID_LINK_PPIXEL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MHL_DCAP_VID_LINK_ISLANDS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MHL_DCAP_VID_LINK_VGA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MHL_DCAP_VID_LINK_16BPP 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MHL_DCAP_AUD_LINK_2CH 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MHL_DCAP_AUD_LINK_8CH 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MHL_DCAP_VT_GRAPHICS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MHL_DCAP_VT_PHOTO 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MHL_DCAP_VT_CINEMA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MHL_DCAP_VT_GAMES 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MHL_DCAP_SUPP_VT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MHL_DCAP_LD_DISPLAY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MHL_DCAP_LD_VIDEO 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MHL_DCAP_LD_AUDIO 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MHL_DCAP_LD_MEDIA 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MHL_DCAP_LD_TUNER 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MHL_DCAP_LD_RECORD 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MHL_DCAP_LD_SPEAKER 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MHL_DCAP_LD_GUI 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MHL_DCAP_LD_ALL 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MHL_DCAP_FEATURE_RCP_SUPPORT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MHL_DCAP_FEATURE_RAP_SUPPORT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MHL_DCAP_FEATURE_SP_SUPPORT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MHL_DCAP_FEATURE_UCP_SEND_SUPPOR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MHL_DCAP_FEATURE_UCP_RECV_SUPPORT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MHL_DCAP_FEATURE_RBP_SUPPORT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Extended Device Capabilities Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MHL_XDC_ECBUS_SPEEDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MHL_XDC_TMDS_SPEEDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MHL_XDC_ECBUS_ROLES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MHL_XDC_LOG_DEV_MAPX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MHL_XDC_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MHL_XDC_ECBUS_S_075 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MHL_XDC_ECBUS_S_8BIT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MHL_XDC_ECBUS_S_12BIT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MHL_XDC_ECBUS_D_150 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MHL_XDC_ECBUS_D_8BIT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MHL_XDC_TMDS_000 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MHL_XDC_TMDS_150 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MHL_XDC_TMDS_300 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MHL_XDC_TMDS_600 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* MHL_XDC_ECBUS_ROLES flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MHL_XDC_DEV_HOST 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MHL_XDC_DEV_DEVICE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MHL_XDC_DEV_CHARGER 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MHL_XDC_HID_HOST 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MHL_XDC_HID_DEVICE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* MHL_XDC_LOG_DEV_MAPX flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MHL_XDC_LD_PHONE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Device Status Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MHL_DST_CONNECTED_RDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MHL_DST_LINK_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MHL_DST_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MHL_DST_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Offset of DEVSTAT registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MHL_DST_OFFSET 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MHL_DST_REG(name) (MHL_DST_OFFSET + MHL_DST_##name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MHL_DST_CONN_DCAP_RDY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MHL_DST_CONN_XDEVCAPP_SUPP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MHL_DST_CONN_POW_STAT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MHL_DST_CONN_PLIM_STAT_MASK 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MHL_DST_LM_CLK_MODE_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MHL_DST_LM_CLK_MODE_PACKED_PIXEL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MHL_DST_LM_CLK_MODE_NORMAL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MHL_DST_LM_PATH_EN_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MHL_DST_LM_PATH_ENABLED 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MHL_DST_LM_PATH_DISABLED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MHL_DST_LM_MUTED_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Extended Device Status Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MHL_XDS_CURR_ECBUS_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MHL_XDS_AVLINK_MODE_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MHL_XDS_AVLINK_MODE_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MHL_XDS_MULTI_SINK_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MHL_XDS_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Offset of XDEVSTAT registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MHL_XDS_OFFSET 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MHL_XDS_REG(name) (MHL_XDS_OFFSET + MHL_XDS_##name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* MHL_XDS_REG_CURR_ECBUS_MODE flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MHL_XDS_SLOT_MODE_8BIT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MHL_XDS_SLOT_MODE_6BIT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MHL_XDS_ECBUS_S 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MHL_XDS_ECBUS_D 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MHL_XDS_LINK_CLOCK_75MHZ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MHL_XDS_LINK_CLOCK_150MHZ 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MHL_XDS_LINK_CLOCK_300MHZ 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MHL_XDS_LINK_CLOCK_600MHZ 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MHL_XDS_LINK_STATUS_NO_SIGNAL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MHL_XDS_LINK_STATUS_CRU_LOCKED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MHL_XDS_LINK_STATUS_TMDS_NORMAL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MHL_XDS_LINK_STATUS_TMDS_RESERVED 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MHL_XDS_LINK_RATE_1_5_GBPS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MHL_XDS_LINK_RATE_3_0_GBPS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MHL_XDS_LINK_RATE_6_0_GBPS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MHL_XDS_ATT_CAPABLE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MHL_XDS_SINK_STATUS_1_HPD_LOW 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MHL_XDS_SINK_STATUS_1_HPD_HIGH 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MHL_XDS_SINK_STATUS_2_HPD_LOW 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MHL_XDS_SINK_STATUS_2_HPD_HIGH 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MHL_XDS_SINK_STATUS_3_HPD_LOW 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MHL_XDS_SINK_STATUS_3_HPD_HIGH 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MHL_XDS_SINK_STATUS_4_HPD_LOW 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MHL_XDS_SINK_STATUS_4_HPD_HIGH 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Interrupt Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MHL_INT_RCHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MHL_INT_DCHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MHL_INT_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Offset of DEVSTAT registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MHL_INT_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MHL_INT_REG(name) (MHL_INT_OFFSET + MHL_INT_##name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MHL_INT_RC_DCAP_CHG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MHL_INT_RC_DSCR_CHG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define MHL_INT_RC_REQ_WRT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MHL_INT_RC_GRT_WRT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MHL_INT_RC_3D_REQ 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MHL_INT_RC_FEAT_REQ 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MHL_INT_RC_FEAT_COMPLETE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MHL_INT_DC_EDID_CHG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MHL_ACK = 0x33, /* Command or Data byte acknowledge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MHL_NACK = 0x34, /* Command or Data byte not acknowledge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MHL_ABORT = 0x35, /* Transaction abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MHL_WRITE_STAT = 0xe0, /* Write one status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MHL_SET_INT = 0x60, /* Write one interrupt register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MHL_READ_DEVCAP_REG = 0x61, /* Read one register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MHL_GET_STATE = 0x62, /* Read CBUS revision level from follower */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MHL_GET_VENDOR_ID = 0x63, /* Read vendor ID value from follower */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MHL_SET_HPD = 0x64, /* Set Hot Plug Detect in follower */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MHL_CLR_HPD = 0x65, /* Clear Hot Plug Detect in follower */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MHL_SET_CAP_ID = 0x66, /* Set Capture ID for downstream device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MHL_GET_CAP_ID = 0x67, /* Get Capture ID from downstream device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MHL_MSC_MSG = 0x68, /* VS command to send RCP sub-commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MHL_GET_SC1_ERRORCODE = 0x69, /* Get Vendor-Specific error code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MHL_GET_DDC_ERRORCODE = 0x6A, /* Get DDC channel command error code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MHL_GET_MSC_ERRORCODE = 0x6B, /* Get MSC command error code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MHL_WRITE_BURST = 0x6C, /* Write 1-16 bytes to responder's scratchpad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MHL_GET_SC3_ERRORCODE = 0x6D, /* Get channel 3 command error code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MHL_WRITE_XSTAT = 0x70, /* Write one extended status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MHL_READ_XDEVCAP_REG = 0x71, /* Read one extended devcap register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* let the rest of these float, they are software specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MHL_READ_EDID_BLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MHL_SEND_3D_REQ_OR_FEAT_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MHL_READ_DEVCAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MHL_READ_XDEVCAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* MSC message types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MHL_MSC_MSG_RCP = 0x10, /* RCP sub-command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MHL_MSC_MSG_RCPK = 0x11, /* RCP Acknowledge sub-command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MHL_MSC_MSG_RCPE = 0x12, /* RCP Error sub-command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MHL_MSC_MSG_RAP = 0x20, /* Mode Change Warning sub-command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MHL_MSC_MSG_RAPK = 0x21, /* MCW Acknowledge sub-command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MHL_MSC_MSG_RBP = 0x22, /* Remote Button Protocol sub-command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MHL_MSC_MSG_RBPK = 0x23, /* RBP Acknowledge sub-command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MHL_MSC_MSG_RBPE = 0x24, /* RBP Error sub-command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MHL_MSC_MSG_UCP = 0x30, /* UCP sub-command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MHL_MSC_MSG_UCPK = 0x31, /* UCP Acknowledge sub-command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MHL_MSC_MSG_UCPE = 0x32, /* UCP Error sub-command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MHL_MSC_MSG_RUSB = 0x40, /* Request USB host role */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MHL_MSC_MSG_RUSBK = 0x41, /* Acknowledge request for USB host role */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MHL_MSC_MSG_RHID = 0x42, /* Request HID host role */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MHL_MSC_MSG_RHIDK = 0x43, /* Acknowledge request for HID host role */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MHL_MSC_MSG_ATT = 0x50, /* Request attention sub-command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MHL_MSC_MSG_ATTK = 0x51, /* ATT Acknowledge sub-command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MHL_MSC_MSG_BIST_TRIGGER = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MHL_MSC_MSG_BIST_REQUEST_STAT = 0x61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MHL_MSC_MSG_BIST_READY = 0x62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MHL_MSC_MSG_BIST_STOP = 0x63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* RAP action codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MHL_RAP_POLL 0x00 /* Just do an ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define MHL_RAP_CONTENT_ON 0x10 /* Turn content stream ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MHL_RAP_CONTENT_OFF 0x11 /* Turn content stream OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MHL_RAP_CBUS_MODE_DOWN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MHL_RAP_CBUS_MODE_UP 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* RAPK status codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define MHL_RAPK_NO_ERR 0x00 /* RAP action recognized & supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MHL_RAPK_UNRECOGNIZED 0x01 /* Unknown RAP action code received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define MHL_RAPK_UNSUPPORTED 0x02 /* Rcvd RAP action code not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MHL_RAPK_BUSY 0x03 /* Responder too busy to respond */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Bit masks for RCP messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define MHL_RCP_KEY_RELEASED_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define MHL_RCP_KEY_ID_MASK 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * Error status codes for RCPE messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* No error. (Not allowed in RCPE messages) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define MHL_RCPE_STATUS_NO_ERROR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Unsupported/unrecognized key code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define MHL_RCPE_STATUS_INEFFECTIVE_KEY_CODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Responder busy. Initiator may retry message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define MHL_RCPE_STATUS_BUSY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * Error status codes for RBPE messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* No error. (Not allowed in RBPE messages) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define MHL_RBPE_STATUS_NO_ERROR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Unsupported/unrecognized button code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define MHL_RBPE_STATUS_INEFFECTIVE_BUTTON_CODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Responder busy. Initiator may retry message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define MHL_RBPE_STATUS_BUSY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * Error status codes for UCPE messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* No error. (Not allowed in UCPE messages) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define MHL_UCPE_STATUS_NO_ERROR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Unsupported/unrecognized key code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define MHL_UCPE_STATUS_INEFFECTIVE_KEY_CODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) enum mhl_burst_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MHL_BURST_ID_3D_VIC = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MHL_BURST_ID_3D_DTD = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MHL_BURST_ID_HEV_VIC = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MHL_BURST_ID_HEV_DTDA = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MHL_BURST_ID_HEV_DTDB = 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MHL_BURST_ID_VC_ASSIGN = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MHL_BURST_ID_VC_CONFIRM = 0x39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MHL_BURST_ID_AUD_DELAY = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MHL_BURST_ID_ADT_BURSTID = 0x41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MHL_BURST_ID_BIST_SETUP = 0x51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MHL_BURST_ID_BIST_RETURN_STAT = 0x52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MHL_BURST_ID_EMSC_SUPPORT = 0x61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MHL_BURST_ID_HID_PAYLOAD = 0x62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MHL_BURST_ID_BLK_RCV_BUFFER_INFO = 0x63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MHL_BURST_ID_BITS_PER_PIXEL_FMT = 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct mhl_burst_blk_rcv_buffer_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) __be16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) __le16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct mhl3_burst_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) __be16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u8 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u8 total_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u8 sequence_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct mhl_burst_bits_per_pixel_fmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct mhl3_burst_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u8 num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u8 stream_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u8 pixel_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) } __packed desc[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct mhl_burst_emsc_support {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct mhl3_burst_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u8 num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) __be16 burst_id[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct mhl_burst_audio_descr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct mhl3_burst_header hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u8 short_desc[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * MHL3 infoframe related definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define MHL3_IEEE_OUI 0x7ca61d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define MHL3_INFOFRAME_SIZE 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) enum mhl3_video_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MHL3_VIDEO_FORMAT_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MHL3_VIDEO_FORMAT_3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MHL3_VIDEO_FORMAT_MULTI_VIEW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) MHL3_VIDEO_FORMAT_DUAL_3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) enum mhl3_3d_format_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MHL3_3D_FORMAT_TYPE_FS, /* frame sequential */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MHL3_3D_FORMAT_TYPE_TB, /* top-bottom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MHL3_3D_FORMAT_TYPE_LR, /* left-right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MHL3_3D_FORMAT_TYPE_FS_TB, /* frame sequential, top-bottom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MHL3_3D_FORMAT_TYPE_FS_LR, /* frame sequential, left-right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MHL3_3D_FORMAT_TYPE_TB_LR /* top-bottom, left-right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct mhl3_infoframe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned char version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) enum mhl3_video_format video_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) enum mhl3_3d_format_type format_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) bool sep_audio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int hev_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int av_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #endif /* __MHL_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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